1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
|
/*
* (C) 2003-2004 Linux Networx
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/pcix.h>
#include <pc80/mc146818rtc.h>
#include <delay.h>
#include "pxhd.h"
static void pxhd_enable(device_t dev)
{
device_t bridge;
uint16_t value;
if ((dev->path.pci.devfn & 1) == 0) {
/* Can we enable/disable the bridges? */
return;
}
bridge = dev_find_slot(dev->bus->secondary, dev->path.pci.devfn & ~1);
if (!bridge) {
printk_err("Cannot find bridge for ioapic: %s\n",
dev_path(dev));
return;
}
value = pci_read_config16(bridge, 0x40);
value &= ~(1 << 13);
if (!dev->enabled) {
value |= (1 << 13);
}
pci_write_config16(bridge, 0x40, value);
}
#define NMI_OFF 0
static unsigned int pxhd_scan_bridge(device_t dev, unsigned int max)
{
int bus_100Mhz = 0;
dev->link[0].dev = dev;
dev->links = 1;
get_option(&bus_100Mhz, "pxhd_bus_speed_100");
if(bus_100Mhz) {
uint16_t word;
printk_debug("setting pxhd bus to 100 Mhz\n");
/* set to pcix 100 mhz */
word = pci_read_config16(dev, 0x40);
word &= ~(3 << 14);
word |= (1 << 14);
word &= ~(3 << 9);
word |= (2 << 9);
pci_write_config16(dev, 0x40, word);
/* reset the bus to make the new frequencies effective */
pci_bus_reset(&dev->link[0]);
}
return pcix_scan_bridge(dev, max);
}
static void pcix_init(device_t dev)
{
uint32_t dword;
uint16_t word;
uint8_t byte;
int nmi_option;
/* Bridge control ISA enable */
pci_write_config8(dev, 0x3e, 0x07);
#if 0
/* Enable memory write and invalidate ??? */
byte = pci_read_config8(dev, 0x04);
byte |= 0x10;
pci_write_config8(dev, 0x04, byte);
/* Set drive strength */
word = pci_read_config16(dev, 0xe0);
word = 0x0404;
pci_write_config16(dev, 0xe0, word);
word = pci_read_config16(dev, 0xe4);
word = 0x0404;
pci_write_config16(dev, 0xe4, word);
/* Set impedance */
word = pci_read_config16(dev, 0xe8);
word = 0x0404;
pci_write_config16(dev, 0xe8, word);
/* Set discard unrequested prefetch data */
word = pci_read_config16(dev, 0x4c);
word |= 1;
pci_write_config16(dev, 0x4c, word);
/* Set split transaction limits */
word = pci_read_config16(dev, 0xa8);
pci_write_config16(dev, 0xaa, word);
word = pci_read_config16(dev, 0xac);
pci_write_config16(dev, 0xae, word);
/* Set up error reporting, enable all */
/* system error enable */
dword = pci_read_config32(dev, 0x04);
dword |= (1<<8);
pci_write_config32(dev, 0x04, dword);
/* system and error parity enable */
dword = pci_read_config32(dev, 0x3c);
dword |= (3<<16);
pci_write_config32(dev, 0x3c, dword);
/* NMI enable */
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if(nmi_option) {
dword = pci_read_config32(dev, 0x44);
dword |= (1<<0);
pci_write_config32(dev, 0x44, dword);
}
/* Set up CRC flood enable */
dword = pci_read_config32(dev, 0xc0);
if(dword) { /* do device A only */
dword = pci_read_config32(dev, 0xc4);
dword |= (1<<1);
pci_write_config32(dev, 0xc4, dword);
dword = pci_read_config32(dev, 0xc8);
dword |= (1<<1);
pci_write_config32(dev, 0xc8, dword);
}
return;
#endif
}
static struct device_operations pcix_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
.init = pcix_init,
.scan_bus = pxhd_scan_bridge,
.reset_bus = pci_bus_reset,
.ops_pci = 0,
};
static const struct pci_driver pcix_driver __pci_driver = {
.ops = &pcix_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x0329,
};
static const struct pci_driver pcix_driver2 __pci_driver = {
.ops = &pcix_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x032a,
};
#define ALL (0xff << 24)
#define NONE (0)
#define DISABLED (1 << 16)
#define ENABLED (0 << 16)
#define TRIGGER_EDGE (0 << 15)
#define TRIGGER_LEVEL (1 << 15)
#define POLARITY_HIGH (0 << 13)
#define POLARITY_LOW (1 << 13)
#define PHYSICAL_DEST (0 << 11)
#define LOGICAL_DEST (1 << 11)
#define ExtINT (7 << 8)
#define NMI (4 << 8)
#define SMI (2 << 8)
#define INT (1 << 8)
/* IO-APIC virtual wire mode configuration */
/* mask, trigger, polarity, destination, delivery, vector */
static void setup_ioapic(device_t dev)
{
int i;
unsigned long value_low, value_high;
unsigned long ioapic_base;
volatile unsigned long *l;
unsigned interrupts;
ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
l = (unsigned long *) ioapic_base;
/* Enable front side bus delivery */
l[0] = 0x03;
l[4] = 1;
l[0] = 0x01;
interrupts = (l[04] >> 16) & 0xff;
for (i = 0; i < interrupts; i++) {
l[0] = (i * 2) + 0x10;
l[4] = DISABLED;
value_low = l[4];
l[0] = (i * 2) + 0x11;
l[4] = NONE; /* Should this be an address? */
value_high = l[4];
if (value_low == 0xffffffff) {
printk_warning("IO APIC not responding.\n");
return;
}
}
}
static void ioapic_init(device_t dev)
{
uint32_t value;
/* Enable bus mastering so IOAPICs work */
value = pci_read_config16(dev, PCI_COMMAND);
value |= PCI_COMMAND_MASTER;
pci_write_config16(dev, PCI_COMMAND, value);
setup_ioapic(dev);
}
static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations intel_ops_pci = {
.set_subsystem = intel_set_subsystem,
};
static struct device_operations ioapic_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = ioapic_init,
.scan_bus = 0,
.enable = pxhd_enable,
.ops_pci = &intel_ops_pci,
};
static const struct pci_driver ioapic_driver __pci_driver = {
.ops = &ioapic_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x0326,
};
static const struct pci_driver ioapic2_driver __pci_driver = {
.ops = &ioapic_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x0327,
};
struct chip_operations southbridge_intel_pxhd_ops = {
CHIP_NAME("Intel PXHD Southbridge")
.enable_dev = pxhd_enable,
};
|
