1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
|
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/io.h>
#include <cf9_reset.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <delay.h>
#include <halt.h>
#include <timer.h>
#include "me.h"
#include "pch.h"
static const char *me_ack_values[] = {
[ME_HFS_ACK_NO_DID] = "No DID Ack received",
[ME_HFS_ACK_RESET] = "Non-power cycle reset",
[ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset",
[ME_HFS_ACK_S3] = "Go to S3",
[ME_HFS_ACK_S4] = "Go to S4",
[ME_HFS_ACK_S5] = "Go to S5",
[ME_HFS_ACK_GBL_RESET] = "Global Reset",
[ME_HFS_ACK_CONTINUE] = "Continue to boot"
};
void intel_early_me_status(void)
{
union me_hfs hfs = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS) };
union me_hfs2 hfs2 = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS2) };
intel_me_status(hfs, hfs2);
}
int intel_early_me_init(void)
{
int count;
union me_uma uma;
union me_hfs hfs;
printk(BIOS_INFO, "Intel ME early init\n");
/* Wait for ME UMA SIZE VALID bit to be set */
/* FIXME: ME9 BGW indicates a 5 sec poll timeout. */
for (count = ME_RETRY; count > 0; --count) {
uma.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA);
if (uma.valid)
break;
udelay(ME_DELAY);
}
if (!count) {
printk(BIOS_ERR, "ME is not ready!\n");
return -1;
}
/* Check for valid firmware */
hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
if (hfs.fpt_bad) {
printk(BIOS_WARNING, "ME has bad firmware\n");
return -1;
}
printk(BIOS_INFO, "Intel ME firmware is ready\n");
return 0;
}
bool intel_early_me_cpu_replacement_check(void)
{
printk(BIOS_DEBUG, "ME: Checking whether CPU was replaced... ");
struct stopwatch timer;
stopwatch_init_msecs_expire(&timer, 50);
union me_hfs2 hfs2;
do {
hfs2.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS2);
if (stopwatch_expired(&timer)) {
/* Assume CPU was replaced just in case */
printk(BIOS_DEBUG, "timed out, assuming CPU was replaced\n");
return true;
}
udelay(ME_DELAY);
} while (!hfs2.cpu_replaced_valid);
if (hfs2.warm_reset_request) {
printk(BIOS_DEBUG, "warm reset needed for dynamic fusing\n");
system_reset();
}
printk(BIOS_DEBUG, "%sreplaced\n", hfs2.cpu_replaced_sts ? "" : "not ");
return hfs2.cpu_replaced_sts;
}
int intel_early_me_uma_size(void)
{
union me_uma uma = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA) };
if (uma.valid) {
printk(BIOS_DEBUG, "ME: Requested %uMB UMA\n", uma.size);
return uma.size;
}
printk(BIOS_DEBUG, "ME: Invalid UMA size\n");
return 0;
}
static inline void set_global_reset(int enable)
{
u32 pmir = pci_read_config32(PCH_LPC_DEV, PMIR);
/* CF9GR indicates a Global Reset */
if (enable)
pmir |= PMIR_CF9GR;
else
pmir &= ~PMIR_CF9GR;
pci_write_config32(PCH_LPC_DEV, PMIR, pmir);
}
int intel_early_me_init_done(u8 status)
{
u8 reset;
int count;
u32 mebase_l, mebase_h;
union me_hfs hfs;
union me_did did = {
.init_done = ME_INIT_DONE,
.status = status
};
/* MEBASE from MESEG_BASE[35:20] */
mebase_l = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_L);
mebase_h = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_H) & 0xf;
did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
/* Send message to ME */
printk(BIOS_DEBUG, "ME: Sending Init Done with status: %d, "
"UMA base: 0x%04x\n", status, did.uma_base);
pci_write_config32(PCH_ME_DEV, PCI_ME_H_GS, did.raw);
/*
* The ME firmware does not respond with an ACK when NOMEM or ERROR
* are sent.
*/
if (status == ME_INIT_STATUS_NOMEM || status == ME_INIT_STATUS_ERROR)
return 0;
/* Must wait for ME acknowledgement */
for (count = ME_RETRY; count > 0; --count) {
hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
if (hfs.bios_msg_ack)
break;
udelay(ME_DELAY);
}
if (!count) {
printk(BIOS_ERR, "ME failed to respond\n");
return -1;
}
/* Return the requested BIOS action */
printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n",
me_ack_values[hfs.ack_data]);
/* Check status after acknowledgement */
intel_early_me_status();
reset = 0;
switch (hfs.ack_data) {
case ME_HFS_ACK_CONTINUE:
/* Continue to boot */
return 0;
case ME_HFS_ACK_RESET:
/* Non-power cycle reset */
set_global_reset(0);
reset = 0x06;
break;
case ME_HFS_ACK_PWR_CYCLE:
/* Power cycle reset */
set_global_reset(0);
reset = 0x0e;
break;
case ME_HFS_ACK_GBL_RESET:
/* Global reset */
set_global_reset(1);
reset = 0x0e;
break;
case ME_HFS_ACK_S3:
case ME_HFS_ACK_S4:
case ME_HFS_ACK_S5:
break;
}
/* Perform the requested reset */
if (reset) {
outb(reset, 0xcf9);
halt();
}
return -1;
}
|
