blob: f79e963206d32be1e8caa10a61597dd14c998b63 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
|
##
## This file is part of the coreboot project.
##
## Copyright (C) 2011 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
config SOUTHBRIDGE_INTEL_LYNXPOINT
bool
if SOUTHBRIDGE_INTEL_LYNXPOINT
config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select IOAPIC
select HAVE_HARD_RESET
select HAVE_USBDEBUG
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select SPI_FLASH
select ALT_CBFS_LOAD_PAYLOAD
config INTEL_LYNXPOINT_LP
bool
default n
help
Set this option to y for Lynxpont LP (Haswell ULT).
config EHCI_BAR
hex
default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
default 0xa0
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/intel/lynxpoint/bootblock.c"
config SERIRQ_CONTINUOUS_MODE
bool
default n
help
If you set this option to y, the serial IRQ machine will be
operated in continuous mode.
endif
|
