1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
|
/* SPDX-License-Identifier: GPL-2.0-only */
Field (\_SB.PCI0.LPCB.PCIC, AnyAcc, NoLock, Preserve)
{
Offset (0x60), // Interrupt Routing Registers
PRTA, 8,
PRTB, 8,
PRTC, 8,
PRTD, 8,
}
Name(IRQB, ResourceTemplate(){
IRQ(Level,ActiveLow,Shared){15}
})
Name(IRQP, ResourceTemplate(){
IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 6, 7, 10, 11, 12}
})
/* adapted from ma78gm/dsdt.asl */
#define PCI_INTX_DEV(intx, pinx, uid) \
Device(intx) { \
Name(_HID, EISAID("PNP0C0F")) \
Name(_UID, uid) \
\
Method(_STA, 0) { \
If (pinx & 0x80) { \
Return(0x09) \
} \
Return(0x0B) \
} \
\
Method(_DIS ,0) { \
pinx = 0x80 \
} \
\
Method(_PRS ,0) { \
Return(IRQP) \
} \
\
Method(_CRS ,0) { \
CreateWordField(IRQB, 1, IRQN) \
IRQN = 1 << (pinx & 0x0f) \
Return(IRQB) \
} \
\
Method(_SRS, 1) { \
CreateWordField(ARG0, 1, IRQM) \
\
/* Use lowest available IRQ */ \
FindSetRightBit(IRQM, Local0) \
if (Local0) { \
Local0-- \
} \
pinx = Local0 \
} \
} \
PCI_INTX_DEV(LNKA, PRTA, 1)
PCI_INTX_DEV(LNKB, PRTB, 2)
PCI_INTX_DEV(LNKC, PRTC, 3)
PCI_INTX_DEV(LNKD, PRTD, 4)
|
