blob: f628270b2b1dd4ff1821b98af7c82489ffe3a387 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
|
##
## This file is part of the coreboot project.
##
## Copyright (C) 2011 Google Inc.
## Copyright (C) 2013 Sage Electronic Engineering, LLC.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
config SOUTHBRIDGE_INTEL_FSP_BD82X6X
bool
if SOUTHBRIDGE_INTEL_FSP_BD82X6X
config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select IOAPIC
select HAVE_HARD_RESET
select HAVE_SMI_HANDLER
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select SPI_FLASH
select PER_DEVICE_ACPI_TABLES
config EHCI_BAR
hex
default 0xfef00000
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/intel/fsp_bd82x6x/bootblock.c"
config SERIRQ_CONTINUOUS_MODE
bool
default n
help
If you set this option to y, the serial IRQ machine will be
operated in continuous mode.
config HPET_MIN_TICKS
hex
default 0x80
if HAVE_FSP_BIN
config INCLUDE_ME
bool
default n
help
Include the me.bin and descriptor.bin for Intel PCH.
This is usually required for the PCH.
config ME_PATH
string
depends on INCLUDE_ME
help
The path of the ME and Descriptor files.
config LOCK_MANAGEMENT_ENGINE
bool "Lock Management Engine section"
default n
depends on INCLUDE_ME
help
The Intel Management Engine supports preventing write accesses
from the host to the Management Engine section in the firmware
descriptor. If the ME section is locked, it can only be overwritten
with an external SPI flash programmer. You will want this if you
want to increase security of your ROM image once you are sure
that the ME firmware is no longer going to change.
If unsure, say N.
endif # HAVE_FSP_BIN
endif
|
