blob: 4708f1fa7c9b1426a78c30754a247fcab2708ae0 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
|
##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Advanced Micro Devices, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
config SOUTHBRIDGE_AMD_SB800
bool
select IOAPIC
select HAVE_USBDEBUG
select HAVE_HARD_RESET
if SOUTHBRIDGE_AMD_SB800
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/amd/sb800/bootblock.c"
config SOUTHBRIDGE_AMD_SB800_SKIP_ISA_DMA_INIT
bool
default n
config EHCI_BAR
hex
default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
default 0xe0
endif # SOUTHBRIDGE_AMD_SB800
|
