blob: b47089268afb322b586717acce22725e46df1a3f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
|
config SOC_NVIDIA_TEGRA132
bool
default n
select ARCH_BOOTBLOCK_ARMV4
select BOOTBLOCK_CUSTOM
select ARCH_VERSTAGE_ARMV4
select ARCH_ROMSTAGE_ARMV4
select ARCH_RAMSTAGE_ARMV8_64
select BOOTBLOCK_CONSOLE
select GIC
select HAVE_MONOTONIC_TIMER
select GENERIC_UDELAY
select HAVE_HARD_RESET
select HAVE_UART_SPECIAL
select GENERIC_GPIO_LIB
select UART_OVERRIDE_REFCLK
if SOC_NVIDIA_TEGRA132
config CHROMEOS
select VBOOT_OPROM_MATTERS
config MAINBOARD_DO_DSI_INIT
bool "Use dsi graphics interface"
depends on MAINBOARD_DO_NATIVE_VGA_INIT
default n
help
Initialize dsi display
config MAINBOARD_DO_SOR_INIT
bool "Use dp graphics interface"
depends on MAINBOARD_DO_NATIVE_VGA_INIT
default n
help
Initialize dp display
config MTS_DIRECTORY
string "Directory where MTS microcode files are located"
default "3rdparty/blobs/cpu/nvidia/tegra132/current/prod"
help
Path to directory where MTS microcode files are located.
config TRUSTZONE_CARVEOUT_SIZE_MB
hex "Size of Trust Zone region"
default 0x4
help
Size of Trust Zone area in MiB to reserve in memory map.
config BOOTROM_SDRAM_INIT
bool "SoC BootROM does SDRAM init with full BCT"
default n
help
Use during Ryu LPDDR3 bringup
# Default to 700MHz. This value is based on nv bootloader setting.
config PLLX_KHZ
int
default 700000
endif
|
