blob: 3ce368b95f7cee75fd6c966f86ede534a0991e6a (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
|
config SOC_NVIDIA_TEGRA124
bool
default n
select ARCH_BOOTBLOCK_ARMV4
select ARCH_VERSTAGE_ARMV4
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
select HAVE_UART_SPECIAL
select HAVE_HARD_RESET
select HAVE_MONOTONIC_TIMER
select GENERIC_UDELAY
select BOOTBLOCK_CONSOLE
select ARM_BOOTBLOCK_CUSTOM
select ARM_LPAE
if SOC_NVIDIA_TEGRA124
config BOOTBLOCK_CPU_INIT
string
default "soc/nvidia/tegra124/bootblock.c"
help
CPU/SoC-specific bootblock code. This is useful if the
bootblock must load microcode or copy data from ROM before
searching for the bootblock.
config BOOTBLOCK_ROM_OFFSET
hex
default 0x0
config CBFS_HEADER_ROM_OFFSET
hex "offset of master CBFS header in ROM"
default 0x18000
config CBFS_ROM_OFFSET
hex "offset of CBFS data in ROM"
default 0x18080
config TEGRA124_MODEL_TD570D
bool "TD570D"
config TEGRA124_MODEL_TD580D
bool "TD580D"
config TEGRA124_MODEL_CD570M
bool "CD570M"
config TEGRA124_MODEL_CD580M
bool "CD580M"
# Default to 2GHz, the lowest maximum frequency.
config PLLX_KHZ
int
default 2000000 if TEGRA124_MODEL_TD570D
default 2300000 if TEGRA124_MODEL_TD580D
default 2100000 if TEGRA124_MODEL_CD570M
default 2300000 if TEGRA124_MODEL_CD580M
default 2000000
endif
|