blob: eafd8002297d30aee325b731bc4619d7fc9f1d89 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
|
## SPDX-License-Identifier: GPL-2.0-only
ifeq ($(CONFIG_SOC_INTEL_SKYLAKE_SP),y)
subdirs-y += ../../../../cpu/intel/microcode
subdirs-y += ../../../../cpu/intel/turbo
subdirs-y += ../../../../cpu/x86/lapic
subdirs-y += ../../../../cpu/x86/cache
postcar-y += soc_util.c
romstage-y += soc_util.c
romstage-y += romstage.c
romstage-y += soc_util.c
romstage-y += hob_display.c
romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
ramstage-y += soc_acpi.c
ramstage-y += chip.c
ramstage-y += soc_util.c
ramstage-y += cpu.c
ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
ramstage-y += hob_display.c
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/skx/include -I$(src)/soc/intel/xeon_sp/skx
cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-04
endif ## CONFIG_SOC_INTEL_SKYLAKE_SP
|
