blob: 18e5f2f59a8c88a6fe3ade438c3aac529a4f2b1b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
|
## SPDX-License-Identifier: GPL-2.0-only
if SOC_INTEL_SKYLAKE_SP
config MAINBOARD_USES_FSP2_0
bool
default y
config FSP_HEADER_PATH
string "Location of FSP headers"
depends on MAINBOARD_USES_FSP2_0
default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp"
config MAX_SOCKET
int
default 2
# For 2S config, the number of cpus could be as high as
# 2 threads * 20 cores * 2 sockets
config MAX_CPUS
int
default 80
config PCR_BASE_ADDRESS
hex
default 0xfd000000
help
This option allows you to select MMIO Base Address of sideband bus.
config DCACHE_RAM_BASE
hex
default 0xfe800000
config DCACHE_RAM_SIZE
hex
default 0x200000
config DCACHE_BSP_STACK_SIZE
hex
default 0x10000
config CPU_MICROCODE_CBFS_LOC
hex
default 0xfff0fdc0
config CPU_MICROCODE_CBFS_LEN
hex
default 0x7C00
config HEAP_SIZE
hex
default 0x80000
config IED_REGION_SIZE
hex
default 0x400000
config IFD_CHIPSET
string
default "lbg"
config XEON_SP_HAVE_IIO_IOAPIC
bool
default y
endif
|
