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# SPDX-License-Identifier: GPL-2.0-or-later
source "src/soc/intel/xeon_sp/skx/Kconfig"
source "src/soc/intel/xeon_sp/cpx/Kconfig"
config XEON_SP_COMMON_BASE
bool
config SOC_INTEL_SKYLAKE_SP
bool
select XEON_SP_COMMON_BASE
select PLATFORM_USES_FSP2_0
help
Intel Skylake-SP support
config SOC_INTEL_COOPERLAKE_SP
bool
select XEON_SP_COMMON_BASE
select PLATFORM_USES_FSP2_2
select CACHE_MRC_SETTINGS
help
Intel Cooperlake-SP support
if XEON_SP_COMMON_BASE
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_ALL_STAGES_X86_32
select BOOT_DEVICE_SUPPORTS_WRITES
select CPU_INTEL_COMMON
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_RESET
select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
select FSP_T_XIP
select FSP_M_XIP
select POSTCAR_STAGE
select IOAPIC
select PARALLEL_MP
select PARALLEL_MP_AP_WORK
select PMC_GLOBAL_RESET_ENABLE_LOCK
select INTEL_DESCRIPTOR_MODE_CAPABLE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_PCH_SERVER
select TSC_MONOTONIC_TIMER
select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT
select UDELAY_TSC
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select FSP_CAR
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select SMM_TSEG
select HAVE_SMI_HANDLER
select REG_SCRIPT
select NO_FSP_TEMP_RAM_EXIT
select INTEL_CAR_NEM # For postcar only now
config MAINBOARD_USES_FSP2_0
bool
default y
config USE_FSP2_0_DRIVER
def_bool y
depends on MAINBOARD_USES_FSP2_0
select PLATFORM_USES_FSP2_0
select UDK_202005_BINDING
select POSTCAR_STAGE
config MAX_SOCKET
int
default 2
# For 2S config, the number of cpus could be as high as
# 2 threads * 20 cores * 2 sockets
config MAX_CPUS
int
default 80
config INTEL_ACPI_BASE_ADDRESS
hex
default 0x500
help
IO Address of ACPI.
config INTEL_PCH_PWRM_BASE_ADDRESS
hex
default 0xfe000000
help
PCH PWRM Base address.
config PCR_BASE_ADDRESS
hex
default 0xfd000000
help
This option allows you to select MMIO Base Address of sideband bus.
config DCACHE_BSP_STACK_SIZE
hex
default 0x10000
config MMCONF_BASE_ADDRESS
default 0x80000000
config MMCONF_BUS_NUMBER
default 256
config HEAP_SIZE
hex
default 0x80000
endif ## SOC_INTEL_XEON_SP
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