1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
|
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
#include <intelblocks/gpio.h>
#include <intelblocks/pcr.h>
#include <soc/pcr_ids.h>
#include <soc/pm.h>
static const struct reset_mapping rst_map[] = {
{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30},
{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30},
{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30},
};
static const struct reset_mapping rst_map_com2[] = {
{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30},
{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30},
{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30},
{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30},
};
static const struct pad_group skl_community_com0_groups[] = {
INTEL_GPP(GPP_A0, GPP_A0, GPP_A23), /* GPP A */
INTEL_GPP(GPP_A0, GPP_B0, GPP_B23), /* GPP B */
};
static const struct pad_group skl_community_com1_groups[] = {
INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP C */
#if CONFIG(SKYLAKE_SOC_PCH_H)
INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP D */
INTEL_GPP(GPP_C0, GPP_E0, GPP_E12), /* GPP E */
INTEL_GPP(GPP_C0, GPP_F0, GPP_F23), /* GPP F */
INTEL_GPP(GPP_C0, GPP_G0, GPP_G23), /* GPP G */
INTEL_GPP(GPP_C0, GPP_H0, GPP_H23), /* GPP H */
#else
INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP D */
INTEL_GPP(GPP_C0, GPP_E0, GPP_E23), /* GPP E */
#endif
};
static const struct pad_group skl_community_com3_groups[] = {
#if CONFIG(SKYLAKE_SOC_PCH_H)
INTEL_GPP(GPP_I0, GPP_I0, GPP_I10), /* GPP I */
#else
INTEL_GPP(GPP_F0, GPP_F0, GPP_F23), /* GPP F */
INTEL_GPP(GPP_F0, GPP_G0, GPP_G7), /* GPP G */
#endif
};
static const struct pad_group skl_community_com2_groups[] = {
INTEL_GPP(GPD0, GPD0, GPD11), /* GPP GDP */
};
static const struct pad_community skl_gpio_communities[] = {
{
.port = PID_GPIOCOM0,
.first_pad = GPP_A0,
.last_pad = GPP_B23,
.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPIO_COM0",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = skl_community_com0_groups,
.num_groups = ARRAY_SIZE(skl_community_com0_groups),
}, {
.port = PID_GPIOCOM1,
.first_pad = GPP_C0,
#if CONFIG(SKYLAKE_SOC_PCH_H)
.last_pad = GPP_H23,
#else
.last_pad = GPP_E23,
#endif
.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPIO_COM1",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = skl_community_com1_groups,
.num_groups = ARRAY_SIZE(skl_community_com1_groups),
}, {
.port = PID_GPIOCOM3,
#if CONFIG(SKYLAKE_SOC_PCH_H)
.first_pad = GPP_I0,
.last_pad = GPP_I10,
#else
.first_pad = GPP_F0,
.last_pad = GPP_G7,
#endif
.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPIO_COM3",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = skl_community_com3_groups,
.num_groups = ARRAY_SIZE(skl_community_com3_groups),
}, {
.port = PID_GPIOCOM2,
.first_pad = GPD0,
.last_pad = GPD11,
.num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPIO_COM2",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map_com2,
.num_reset_vals = ARRAY_SIZE(rst_map_com2),
.groups = skl_community_com2_groups,
.num_groups = ARRAY_SIZE(skl_community_com2_groups),
}
};
const struct pad_community *soc_gpio_get_community(size_t *num_communities)
{
*num_communities = ARRAY_SIZE(skl_gpio_communities);
return skl_gpio_communities;
}
const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
{
static const struct pmc_to_gpio_route routes[] = {
{ GPP_A, GPP_A},
{ GPP_B, GPP_B},
{ GPP_C, GPP_C},
{ GPP_D, GPP_D},
{ GPP_E, GPP_E},
{ GPP_F, GPP_F},
{ GPP_G, GPP_G},
#if CONFIG(SKYLAKE_SOC_PCH_H)
{ GPP_H, GPP_H},
{ GPP_I, GPP_I},
#endif
{ GPD, GPD},
};
*num = ARRAY_SIZE(routes);
return routes;
}
uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg,
int dw_reg, uint32_t reg_val)
{
if (CONFIG(SKYLAKE_SOC_PCH_H))
return reg_val;
/*
* For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4
* ~ GPP_F11.
*/
if (cfg->pad >= GPP_F4 && cfg->pad <= GPP_F11 && dw_reg == 1)
reg_val = reg_val & ~(PAD_CFG1_TOL_1V8);
return reg_val;
}
|
