1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
|
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/io.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <bootstate.h>
#include <console/console.h>
#include <console/post_codes.h>
#include <cpu/x86/mp.h>
#include <cpu/x86/smm.h>
#include <device/pci.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/p2sb.h>
#include <intelblocks/pcr.h>
#include <intelblocks/tco.h>
#include <intelblocks/thermal.h>
#include <reg_script.h>
#include <spi-generic.h>
#include <soc/me.h>
#include <soc/p2sb.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
#include <soc/pm.h>
#include <soc/smbus.h>
#include <soc/systemagent.h>
#include <timer.h>
#include "chip.h"
#define PSF_BASE_ADDRESS 0xA00
#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8)
static void pch_disable_heci(void)
{
/* unhide p2sb device */
p2sb_unhide();
/* disable heci */
pcr_or32(PID_PSF1, PSF_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN,
PCR_PSFX_T0_SHDW_PCIEN_FUNDIS);
p2sb_disable_sideband_access();
}
static void pch_finalize_script(struct device *dev)
{
uint32_t reg32;
uint8_t *pmcbase;
config_t *config;
u8 reg8;
tco_lockdown();
/* Display me status before we hide it */
intel_me_status();
pmcbase = pmc_mmio_regs();
config = config_of(dev);
/*
* Set low maximum temp value used for dynamic thermal sensor
* shutdown consideration.
*
* If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the
* thermal sensor when CPU is in a C-state and DTS Temp <= LTT.
*/
pch_thermal_configuration();
/*
* Disable ACPI PM timer based on dt policy
*
* Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
* Disabling ACPI PM timer also switches off TCO
*/
if (config->PmTimerDisabled) {
reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);
reg8 |= (1 << 1);
write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
}
/* Disable XTAL shutdown qualification for low power idle. */
if (config->s0ix_enable) {
reg32 = read32(pmcbase + CIR31C);
reg32 |= XTALSDQDIS;
write32(pmcbase + CIR31C, reg32);
}
/* we should disable Heci1 based on the devicetree policy */
if (config->HeciEnabled == 0)
pch_disable_heci();
/* Hide p2sb device as the OS must not change BAR0. */
p2sb_hide();
}
static void soc_lockdown(struct device *dev)
{
struct soc_intel_skylake_config *config;
u8 reg8;
config = config_of(dev);
/* Global SMI Lock */
if (config->LockDownConfigGlobalSmi == 0) {
reg8 = pci_read_config8(dev, GEN_PMCON_A);
reg8 |= SMI_LOCK;
pci_write_config8(dev, GEN_PMCON_A, reg8);
}
/* Lock chipset memory registers to protect SMM */
mp_run_on_all_cpus(cpu_lt_lock_memory, NULL);
}
static void soc_finalize(void *unused)
{
struct device *dev;
dev = PCH_DEV_PMC;
/* Check if PMC is enabled, else return */
if (dev == NULL)
return;
printk(BIOS_DEBUG, "Finalizing chipset.\n");
pch_finalize_script(dev);
soc_lockdown(dev);
printk(BIOS_DEBUG, "Finalizing SMM.\n");
outb(APM_CNT_FINALIZE, APM_CNT);
/* Indicate finalize step with post code */
post_code(POST_OS_BOOT);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);
|
