1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef DPTF_CPU_PASSIVE
#define DPTF_CPU_PASSIVE 80
#endif
#ifndef DPTF_CPU_CRITICAL
#define DPTF_CPU_CRITICAL 90
#endif
External (\_PR.CP00._PSS, PkgObj)
External (\_SB.MPDL, IntObj)
Device (B0D4)
{
Name(_ADR, 0x00040000) /* Bus 0, Device 4, Function 0 */
Method (_STA)
{
If (LEqual (\DPTE, One)) {
Return (0xF)
} Else {
Return (0x0)
}
}
/*
* Processor Performance Control
*/
Method (_PPC)
{
Return (0)
}
Method (SPPC, 1)
{
Store (Arg0, \PPCM)
/* Notify OS to re-read _PPC limit on each CPU */
\PPCN ()
}
Method (_PSS)
{
If (CondRefOf (\_PR.CP00._PSS)) {
Return (\_PR.CP00._PSS)
} Else {
Return (Package ()
{
Package () { 0, 0, 0, 0, 0, 0 }
})
}
}
Method (_PDL)
{
/* Check for mainboard specific _PDL override */
If (CondRefOf (\_SB.MPDL)) {
Return (\_SB.MPDL)
} ElseIf (CondRefOf (\_PR.CP00._PSS)) {
Store (SizeOf (\_PR.CP00._PSS), Local0)
Decrement (Local0)
Return (Local0)
} Else {
Return (0)
}
}
/* Return PPCC table defined by mainboard */
Method (PPCC)
{
Return (\_SB.MPPC)
}
#ifdef DPTF_CPU_CRITICAL
Method (_CRT)
{
Return (\_SB.DPTF.CTOK (DPTF_CPU_CRITICAL))
}
#endif
#ifdef DPTF_CPU_PASSIVE
Method (_PSV)
{
Return (\_SB.DPTF.CTOK (DPTF_CPU_PASSIVE))
}
#endif
#ifdef DPTF_CPU_ACTIVE_AC0
Method (_AC0)
{
Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC0))
}
#endif
#ifdef DPTF_CPU_ACTIVE_AC1
Method (_AC1)
{
Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC1))
}
#endif
#ifdef DPTF_CPU_ACTIVE_AC2
Method (_AC2)
{
Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC2))
}
#endif
#ifdef DPTF_CPU_ACTIVE_AC3
Method (_AC3)
{
Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC3))
}
#endif
#ifdef DPTF_CPU_ACTIVE_AC4
Method (_AC4)
{
Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC4))
}
#endif
}
|
