blob: 42c2de9a7c80b32cf38fa1c4f7a083ebd385b769 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <arch/io.h>
#include <baytrail/pmc.h>
#include <baytrail/reset.h>
void cold_reset(void)
{
/* S0->S5->S0 trip. */
outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
}
void warm_reset(void)
{
/* PMC_PLTRST# asserted. */
outb(RST_CPU | SYS_RST, RST_CNT);
}
void soft_reset(void)
{
/* Sends INIT# to CPU */
outb(RST_CPU, RST_CNT);
}
void hard_reset(void)
{
/* Don't power cycle on hard_reset(). It's not really clear what the
* semantics should be for the meaning of hard_reset(). */
warm_reset();
}
|
