blob: 549ea55d19486bada35a119505825de7b9dd99b9 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
|
##
## This file is part of the coreboot project.
##
## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config SOC_INTEL_FSP_BAYTRAIL
bool
help
Bay Trail I part support using the Intel FSP.
if SOC_INTEL_FSP_BAYTRAIL
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select HAVE_SMI_HANDLER
select HAVE_HARD_RESET
select RELOCATABLE_MODULES
select PARALLEL_MP
select REG_SCRIPT
select SMM_TSEG
select SMP
select SPI_FLASH
select SSE2
select TSC_CONSTANT_RATE
select TSC_SYNC_MFENCE
select UDELAY_TSC
select SUPPORT_CPU_UCODE_IN_CBFS
select HAVE_INTEL_FIRMWARE
select HAVE_SPI_CONSOLE_SUPPORT
# Microcode header files are delivered in FSP package
select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN
config SOC_INTEL_FSP_BAYTRAIL_MD
bool
default n
config BOOTBLOCK_CPU_INIT
string
default "soc/intel/fsp_baytrail/bootblock/bootblock.c"
config MMCONF_BASE_ADDRESS
hex
default 0xe0000000
config MAX_CPUS
int
default 4
config CPU_ADDR_BITS
int
default 36
config SMM_TSEG_SIZE
hex
default 0x800000
help
This is set by the FSP
config SMM_RESERVED_SIZE
hex
default 0x100000
config VGA_BIOS_ID
string
default "8086,0f31"
help
This is the default PCI ID for the Bay Trail graphics
devices. This string names the vbios ROM in cbfs.
config ENABLE_BUILTIN_COM1
bool "Enable built-in legacy Serial Port"
help
The Baytrail SOC has one legacy serial port. Choose this option to
configure the pads and enable it. This serial port can be used for
the debug console.
config VGA_BIOS_FILE
string
default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS
config CPU_MICROCODE_HEADER_FILES
string
default "../intel/cpu/baytrail/microcode/M0130673322.h ../intel/cpu/baytrail/microcode/M0130679901.h ../intel/cpu/baytrail/microcode/M0230672228.h"
## Baytrail Specific FSP Kconfig
source src/soc/intel/fsp_baytrail/fsp/Kconfig
endif #SOC_INTEL_FSP_BAYTRAIL
|
