blob: 2f0840847bec18690bb4c6d179e9e918e3ef4076 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
|
config SOC_INTEL_COMMON_BLOCK_PMC
depends on SOC_INTEL_COMMON_BLOCK_GPIO
depends on ACPI_INTEL_HARDWARE_SLEEP_VALUES
bool
help
Intel Processor common code for Power Management controller(PMC)
subsystem
choice
prompt "System Power State after Failure"
default POWER_STATE_ON_AFTER_FAILURE
config POWER_STATE_OFF_AFTER_FAILURE
bool "S5 Soft Off"
help
Choose this option if you want to keep system into
S5 after reapplying power after failure
config POWER_STATE_ON_AFTER_FAILURE
bool "S0 Full On"
help
Choose this option if you want to keep system into
S0 after reapplying power after failure
config POWER_STATE_PREVIOUS_AFTER_FAILURE
bool "Keep Previous State"
help
Choose this option if you want to keep system into
same power state as before failure even after reapplying
power
endchoice
config PMC_INVALID_READ_AFTER_WRITE
bool
default n
help
Enable this for PMC devices where a read back of ACPI BAR and
IO access bit does not return the previously written value.
config PMC_GLOBAL_RESET_ENABLE_LOCK
bool
help
Enable this for PMC devices where the reset configuration
and lock register is located under PMC BASE at offset ETR.
Note that the reset register is still at 0xCF9 this only
controls the enable and lock feature.
|
