1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
|
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/cpu.h>
#include <console/console.h>
#include <device/pci.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/mp.h>
#include <cpu/x86/msr.h>
#include <cpu/intel/smm_reloc.h>
#include <cpu/intel/turbo.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/mp_init.h>
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
#include <soc/systemagent.h>
#include <cpu/x86/mtrr.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/common/common.h>
#include "chip.h"
static void soc_fsp_load(void)
{
fsps_load();
}
static void configure_misc(void)
{
msr_t msr;
config_t *conf = config_of_soc();
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
wrmsr(IA32_MISC_ENABLE, msr);
/* Set EIST status */
cpu_set_eist(conf->eist_enable);
/* Disable Thermal interrupts */
msr.lo = 0;
msr.hi = 0;
wrmsr(IA32_THERM_INTERRUPT, msr);
/* Enable package critical interrupt only */
msr.lo = 1 << 4;
msr.hi = 0;
wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
/* Enable PROCHOT */
msr = rdmsr(MSR_POWER_CTL);
msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/
msr.lo |= (1 << 23); /* Lock it */
wrmsr(MSR_POWER_CTL, msr);
}
static void configure_c_states(void)
{
msr_t msr;
/* C-state Interrupt Response Latency Control 1 - package C6/C7 short */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr);
/* C-state Interrupt Response Latency Control 2 - package C6/C7 long */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr);
/* C-state Interrupt Response Latency Control 3 - package C8 */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_32768_NS |
C_STATE_LATENCY_CONTROL_3_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);
/* C-state Interrupt Response Latency Control 4 - package C9 */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_32768_NS |
C_STATE_LATENCY_CONTROL_4_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);
/* C-state Interrupt Response Latency Control 5 - package C10 */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_32768_NS |
C_STATE_LATENCY_CONTROL_5_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
}
/* All CPUs including BSP will run the following function. */
void soc_core_init(struct device *cpu)
{
/* Clear out pending MCEs */
/* TODO(adurbin): This should only be done on a cold boot. Also, some
* of these banks are core vs package scope. For now every CPU clears
* every bank. */
mca_configure();
/* Enable the local CPU apics */
enable_lapic_tpr();
setup_lapic();
/* Configure c-state interrupt response time */
configure_c_states();
/* Configure Enhanced SpeedStep and Thermal Sensors */
configure_misc();
set_aesni_lock();
enable_pm_timer_emulation();
/* Enable Direct Cache Access */
configure_dca_cap();
/* Set energy policy */
set_energy_perf_bias(ENERGY_POLICY_NORMAL);
/* Enable Turbo */
enable_turbo();
/* Enable Vmx */
set_vmx_and_lock();
}
static void per_cpu_smm_trigger(void)
{
/* Relocate the SMM handler. */
smm_relocate();
}
static void post_mp_init(void)
{
/* Set Max Ratio */
cpu_set_max_ratio();
/*
* Now that all APs have been relocated as well as the BSP let SMIs
* start flowing.
*/
global_smi_enable_no_pwrbtn();
/* Lock down the SMRAM space. */
smm_lock();
}
static const struct mp_ops mp_ops = {
/*
* Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP,
* that are set prior to ramstage.
* Real MTRRs programming are being done after resource allocation.
*/
.pre_mp_init = soc_fsp_load,
.get_cpu_count = get_cpu_count,
.get_smm_info = smm_info,
.get_microcode_info = get_microcode_info,
.pre_mp_smm_init = smm_initialize,
.per_cpu_smm_trigger = per_cpu_smm_trigger,
.relocation_handler = smm_relocation_handler,
.post_mp_init = post_mp_init,
};
void soc_init_cpus(struct bus *cpu_bus)
{
if (mp_init_with_smm(cpu_bus, &mp_ops))
printk(BIOS_ERR, "MP initialization failure.\n");
/* Thermal throttle activation offset */
configure_tcc_thermal_target();
}
int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
{
msr_t msr1;
msr_t msr2;
/*
* If PRMRR/SGX is supported the FIT microcode load will set the msr
* 0x08b with the Patch revision id one less than the id in the
* microcode binary. The PRMRR support is indicated in the MSR
* MTRRCAP[12]. If SGX is not enabled, check and avoid reloading the
* same microcode during CPU initialization. If SGX is enabled, as
* part of SGX BIOS initialization steps, the same microcode needs to
* be reloaded after the core PRMRR MSRs are programmed.
*/
msr1 = rdmsr(MTRR_CAP_MSR);
msr2 = rdmsr(MSR_PRMRR_PHYS_BASE);
if (msr2.lo && (current_patch_id == new_patch_id - 1))
return 0;
return (msr1.lo & MTRR_CAP_PRMRR) &&
(current_patch_id == new_patch_id - 1);
}
|
