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config SOC_INTEL_BRASWELL
bool
help
Braswell M/D part support.
if SOC_INTEL_BRASWELL
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_BOOTBLOCK_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select CACHE_MRC_SETTINGS
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
select COLLECT_TIMESTAMPS
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
select HAVE_MONOTONIC_TIMER
select HAVE_SMI_HANDLER
select HAVE_HARD_RESET
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select RELOCATABLE_MODULES
select PARALLEL_MP
select PCIEXP_ASPM
select PCIEXP_CLK_PM
select PCIEXP_COMMON_CLOCK
select PLATFORM_USES_FSP1_1
select REG_SCRIPT
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_RESET
select SMM_TSEG
select SMP
select SPI_FLASH
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select TSC_SYNC_MFENCE
select UDELAY_TSC
select USE_GENERIC_FSP_CAR_INC
select HAVE_INTEL_FIRMWARE
select HAVE_SPI_CONSOLE_SUPPORT
config BOOTBLOCK_CPU_INIT
string
default "soc/intel/braswell/bootblock/bootblock.c"
config MMCONF_BASE_ADDRESS
hex "PCIe CFG Base Address"
default 0xe0000000
config MAX_CPUS
int
default 4
config CPU_ADDR_BITS
int
default 36
config SMM_TSEG_SIZE
hex
default 0x800000
config SMM_RESERVED_SIZE
hex
default 0x100000
# Cache As RAM region layout:
#
# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE
# | Stack |\
# | | | * DCACHE_RAM_ROMSTAGE_STACK_SIZE
# | v |/
# +-------------+
# | ^ |
# | | |
# | CAR Globals |
# +-------------+ DCACHE_RAM_BASE
#
config DCACHE_RAM_BASE
hex "Temporary RAM Base Address"
default 0xfef00000
config DCACHE_RAM_SIZE
hex "Temporary RAM Size"
default 0x4000
help
The size of the cache-as-ram region required during bootblock
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
must add up to a power of 2.
config DCACHE_RAM_ROMSTAGE_STACK_SIZE
hex
default 0x800
help
The amount of anticipated stack usage from the data cache
during pre-ram rom stage execution.
config RESET_ON_INVALID_RAMSTAGE_CACHE
bool "Reset the system on S3 wake when ramstage cache invalid."
default n
depends on RELOCATABLE_RAMSTAGE
help
The haswell romstage code caches the loaded ramstage program
in SMM space. On S3 wake the romstage will copy over a fresh
ramstage that was cached in the SMM space. This option determines
the action to take when the ramstage cache is invalid. If selected
the system will reset otherwise the ramstage will be reloaded from
cbfs.
config ENABLE_BUILTIN_COM1
bool "Enable builtin COM1 Serial Port"
default n
help
The PMC has a legacy COM1 serial port. Choose this option to
configure the pads and enable it. This serial port can be used for
the debug console.
config HAVE_IFD_BIN
def_bool n
config BUILD_WITH_FAKE_IFD
def_bool !HAVE_IFD_BIN
config HAVE_ME_BIN
def_bool n
config IED_REGION_SIZE
hex
default 0x400000
config CHIPSET_BOOTBLOCK_INCLUDE
string
default "soc/intel/braswell/bootblock/timestamp.inc"
endif
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