1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
|
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <intelblocks/gpio.h>
#include <intelblocks/pcr.h>
#include <soc/pcr_ids.h>
#include <soc/pmc.h>
#define DEFAULT_VW_BASE 0x10
/*
* This file is created based on Intel Alder Lake Processor PCH Datasheet
* Document number: 630094, Chapter number: 27
* Document number: 630603, Chapter number: 16
*/
static const struct reset_mapping rst_map_gpp[] = {
{ .logical = PAD_RESET(PWROK), .chipset = 0U << 30 },
{ .logical = PAD_RESET(DEEP), .chipset = 1U << 30 },
{ .logical = PAD_RESET(PLTRST), .chipset = 2U << 30 },
};
static const struct reset_mapping rst_map_gpd[] = {
{ .logical = PAD_RESET(PWROK), .chipset = 0U << 30 },
{ .logical = PAD_RESET(DEEP), .chipset = 1U << 30 },
{ .logical = PAD_RESET(PLTRST), .chipset = 2U << 30 },
{ .logical = PAD_RESET(RSMRST), .chipset = 3U << 30 },
};
/*
* The GPIO pinctrl driver for Alder Lake on Linux expects 32 GPIOs per pad
* group, regardless of whether or not there is a physical pad for each
* exposed GPIO number.
*
* This results in the OS having a sparse GPIO map, and devices that need
* to export an ACPI GPIO must use the OS expected number.
*
* Not all pins are usable as GPIO and those groups do not have a pad base.
*/
static const struct pad_group adl_community0_groups[] = {
INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_B25, 0), /* GPP_B */
INTEL_GPP_BASE(GPP_B0, GPP_T0, GPP_T15, 32), /* GPP_T */
INTEL_GPP_BASE(GPP_B0, GPP_A0, GPP_ESPI_CLK_LOOPBK, 64), /* GPP_A */
};
static const struct vw_entries adl_community0_vw[] = {
{GPP_A0, GPP_A23},
{GPP_B0, GPP_B23},
};
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
static const struct pad_group adl_community1_groups[] = {
INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96), /* GPP_S */
INTEL_GPP_BASE(GPP_S0, GPP_I0, GPP_I19, 128), /* GPP_I */
INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 160), /* GPP_H */
INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 192), /* GPP_D */
INTEL_GPP(GPP_S0, GPP_VGPIO_0, GPP_VGPIO_THC1), /* vGPIO */
};
#else
static const struct pad_group adl_community1_groups[] = {
INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96), /* GPP_S */
INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 128), /* GPP_H */
INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 160), /* GPP_D */
INTEL_GPP(GPP_S0, GPP_CPU_RSVD_1, GPP_CPU_RSVD_24), /* GPP_CPU_RSVD */
INTEL_GPP(GPP_S0, GPP_VGPIO_0, GPP_VGPIO_37), /* vGPIO */
};
#endif
static const struct vw_entries adl_community1_vw[] = {
{GPP_D0, GPP_D19},
{GPP_H0, GPP_H23},
};
/* This community is not visible to the OS */
static const struct pad_group adl_community2_groups[] = {
INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB), /* GPD */
};
/* This community is not visible to the OS */
static const struct pad_group adl_community3_groups[] = {
INTEL_GPP(GPP_CPU_RSVD_25, GPP_CPU_RSVD_25, GPP_vGPIO_PCIE_83), /* vGPIO_PCIE */
};
static const struct pad_group adl_community4_groups[] = {
INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256), /* GPP_C */
INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK, 288), /* GPP_F */
INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB), /* GPP_HVMOS */
INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK, 320), /* GPP_E */
};
static const struct vw_entries adl_community4_vw[] = {
{GPP_F0, GPP_F23},
{GPP_C0, GPP_C23},
{GPP_E0, GPP_E23},
};
static const struct pad_group adl_community5_groups[] = {
INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 352), /* GPP_R */
INTEL_GPP(GPP_R0, GPP_SPI0_IO_2, GPP_SPI0_CLK), /* GPP_SPI0 */
};
static const struct pad_community adl_communities[] = {
[COMM_0] = { /* GPP B, T, A */
.port = PID_GPIOCOM0,
.cpu_port = PID_CPU_GPIOCOM0,
.first_pad = GPIO_COM0_START,
.last_pad = GPIO_COM0_END,
.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPP_BTA",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map_gpp,
.num_reset_vals = ARRAY_SIZE(rst_map_gpp),
.groups = adl_community0_groups,
.num_groups = ARRAY_SIZE(adl_community0_groups),
.vw_base = DEFAULT_VW_BASE,
.vw_entries = adl_community0_vw,
.num_vw_entries = ARRAY_SIZE(adl_community0_vw),
},
[COMM_1] = { /* GPP S, D, H for ADL-P/M
GPP S, I, D, H for ADL-N */
.port = PID_GPIOCOM1,
.cpu_port = PID_CPU_GPIOCOM1,
.first_pad = GPIO_COM1_START,
.last_pad = GPIO_COM1_END,
.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
.name = "GPP_SIHD",
#else
.name = "GPP_SDH",
#endif
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map_gpp,
.num_reset_vals = ARRAY_SIZE(rst_map_gpp),
.groups = adl_community1_groups,
.num_groups = ARRAY_SIZE(adl_community1_groups),
.vw_base = DEFAULT_VW_BASE,
.vw_entries = adl_community1_vw,
.num_vw_entries = ARRAY_SIZE(adl_community1_vw),
},
[COMM_2] = { /* GPD */
.port = PID_GPIOCOM2,
.first_pad = GPIO_COM2_START,
.last_pad = GPIO_COM2_END,
.num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPD",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map_gpd,
.num_reset_vals = ARRAY_SIZE(rst_map_gpd),
.groups = adl_community2_groups,
.num_groups = ARRAY_SIZE(adl_community2_groups),
},
[COMM_3] = { /* vGPIO */
.port = PID_GPIOCOM3,
.cpu_port = PID_CPU_GPIOCOM3,
.first_pad = GPIO_COM3_START,
.last_pad = GPIO_COM3_END,
.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPP_VGPIO",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map_gpp,
.num_reset_vals = ARRAY_SIZE(rst_map_gpp),
.groups = adl_community3_groups,
.num_groups = ARRAY_SIZE(adl_community3_groups),
},
[COMM_4] = { /* GPP F, C, HVMOS, E */
.port = PID_GPIOCOM4,
.cpu_port = PID_CPU_GPIOCOM4,
.first_pad = GPIO_COM4_START,
.last_pad = GPIO_COM4_END,
.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPP_FCE",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map_gpp,
.num_reset_vals = ARRAY_SIZE(rst_map_gpp),
.groups = adl_community4_groups,
.num_groups = ARRAY_SIZE(adl_community4_groups),
.vw_base = DEFAULT_VW_BASE,
.vw_entries = adl_community4_vw,
.num_vw_entries = ARRAY_SIZE(adl_community4_vw),
},
[COMM_5] = { /* GPP R, SPI0 */
.port = PID_GPIOCOM5,
.cpu_port = PID_CPU_GPIOCOM5,
.first_pad = GPIO_COM5_START,
.last_pad = GPIO_COM5_END,
.num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPP_RSPI0",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map_gpp,
.num_reset_vals = ARRAY_SIZE(rst_map_gpp),
.groups = adl_community5_groups,
.num_groups = ARRAY_SIZE(adl_community5_groups),
}
};
const struct pad_community *soc_gpio_get_community(size_t *num_communities)
{
*num_communities = ARRAY_SIZE(adl_communities);
return adl_communities;
}
const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
{
static const struct pmc_to_gpio_route routes[] = {
{ PMC_GPP_B, GPP_B },
{ PMC_GPP_T, GPP_T },
{ PMC_GPP_A, GPP_A },
{ PMC_GPP_S, GPP_S },
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
{ PMC_GPP_I, GPP_I },
#endif
{ PMC_GPP_H, GPP_H },
{ PMC_GPP_D, GPP_D },
{ PMC_GPD, GPD },
{ PMC_GPP_C, GPP_C },
{ PMC_GPP_F, GPP_F },
{ PMC_GPP_E, GPP_E },
{ PMC_GPP_R, GPP_R },
};
*num = ARRAY_SIZE(routes);
return routes;
};
/* GPIOs controllable by non-host (x86) agent, eg. ISH, THC, etc */
static const struct gpio_lock_config gpios_to_lock[] = {
{ GPP_A16, GPIO_LOCK_CONFIG }, /* ISH_GP5 NF4 */
{ GPP_B3, GPIO_LOCK_CONFIG }, /* ISH_GP4B NF4 (not avail in ADL PCH-M) */
{ GPP_B4, GPIO_LOCK_CONFIG }, /* ISH_GP5B NF4 (not avail in ADL PCH-M) */
{ GPP_B5, GPIO_LOCK_CONFIG }, /* ISH_I2C0_SDA NF1 */
{ GPP_B6, GPIO_LOCK_CONFIG }, /* ISH_I2C0_SCL NF1 */
{ GPP_B7, GPIO_LOCK_CONFIG }, /* ISH_I2C1_SDA NF1 */
{ GPP_B8, GPIO_LOCK_CONFIG }, /* ISH_I2C1_SCL NF1 */
{ GPP_B14, GPIO_LOCK_CONFIG }, /* ISH_GP6 NF5 */
{ GPP_B15, GPIO_LOCK_CONFIG }, /* ISH_GP7 NF5 */
{ GPP_B16, GPIO_LOCK_CONFIG }, /* ISH_I2C2_SDA NF4 */
{ GPP_B17, GPIO_LOCK_CONFIG }, /* ISH_I2C2_SCL NF4 */
{ GPP_D0, GPIO_LOCK_CONFIG }, /* ISH_GP0 NF1 */
{ GPP_D1, GPIO_LOCK_CONFIG }, /* ISH_GP1 NF1 */
{ GPP_D2, GPIO_LOCK_CONFIG }, /* ISH_GP2 NF1 */
{ GPP_D3, GPIO_LOCK_CONFIG }, /* ISH_GP3 NF1 */
{ GPP_D9, GPIO_LOCK_CONFIG }, /* ISH_SPI_CS# NF1 */
{ GPP_D10, GPIO_LOCK_CONFIG }, /* ISH_SPI_CLK NF1 */
{ GPP_D11, GPIO_LOCK_CONFIG }, /* ISH_SPI_MISO NF1 */
{ GPP_D12, GPIO_LOCK_CONFIG }, /* ISH_SPI_MOSI NF1 */
{ GPP_D13, GPIO_LOCK_CONFIG }, /* ISH_UART0_RXD NF1 */
{ GPP_D14, GPIO_LOCK_CONFIG }, /* ISH_UART0_TXD NF1 */
{ GPP_D15, GPIO_LOCK_CONFIG }, /* ISH_UART0_RTS# NF1 */
{ GPP_D16, GPIO_LOCK_CONFIG }, /* ISH_UART0_CTS# NF1 */
{ GPP_D17, GPIO_LOCK_CONFIG }, /* ISH_UART1_RXD NF2 */
{ GPP_D18, GPIO_LOCK_CONFIG }, /* ISH_UART1_TXD NF2 */
{ GPP_E9, GPIO_LOCK_CONFIG }, /* ISH_GP4 NF2 */
{ GPP_H12, GPIO_LOCK_CONFIG }, /* ISH_GP6B NF4 */
{ GPP_H13, GPIO_LOCK_CONFIG }, /* ISH_GP7B NF4 */
{ GPP_E1, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO2 NF2 */
{ GPP_E2, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO3 NF2 */
{ GPP_E6, GPIO_LOCK_CONFIG }, /* THC0_SPI1_RST# NF2 */
{ GPP_E10, GPIO_LOCK_CONFIG }, /* THC0_SPI1_CS# NF2 */
{ GPP_E11, GPIO_LOCK_CONFIG }, /* THC0_SPI1_CLK NF2 */
{ GPP_E12, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO1 NF2 */
{ GPP_E13, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO0 NF2 */
{ GPP_E17, GPIO_LOCK_CONFIG }, /* THC0_SPI1_INT# NF2 */
{ GPP_F11, GPIO_LOCK_CONFIG }, /* THC1_SPI2_CLK NF3 */
{ GPP_F12, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO0 NF3 */
{ GPP_F13, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO1 NF3 */
{ GPP_F14, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO2 NF3 */
{ GPP_F15, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO3 NF3 */
{ GPP_F16, GPIO_LOCK_CONFIG }, /* THC1_SPI2_CS# NF3 */
{ GPP_F17, GPIO_LOCK_CONFIG }, /* THC1_SPI2_RST# NF3 */
{ GPP_F18, GPIO_LOCK_CONFIG }, /* THC1_SPI2_INT# NF3 */
{ GPP_H3, GPIO_LOCK_CONFIG }, /* SX_EXIT_HOLDOFF# NF1 */
};
const struct gpio_lock_config *soc_gpio_lock_config(size_t *num)
{
*num = ARRAY_SIZE(gpios_to_lock);
return gpios_to_lock;
}
|
