blob: 632e38e45956c17f8f744856bbfaa00c6a236761 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
|
/*
* This file is part of the coreboot project.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SOC_CAVIUM_CN81XX_INCLUDE_SOC_SOC_H
#define __SOC_CAVIUM_CN81XX_INCLUDE_SOC_SOC_H
#include <stdint.h>
#include <types.h>
/* MIO BOOT Registers */
struct cn81xx_mio_boot {
u8 rsvd0[0xb0];
u64 thr;
u8 rsvd1[0x8];
u64 pin_defs;
u8 rsvd2[0x8];
u64 ap_jump;
u64 rom_limit;
u8 rsvd3[0x18];
u64 bist_stat;
};
check_member(cn81xx_mio_boot, bist_stat, 0xf8);
/*
* 0 = Board supplies 100MHz to DLM_REF_CLK
* 1 = bOard supplies 50MHz to PLL_REFCLK
* */
#define MIO_BOOT_PIN_DEFS_UART0_RTS (1 << 16)
#define MIO_BOOT_PIN_DEFS_UART1_RTS (1 << 17)
#endif /* ! __SOC_CAVIUM_CN81XX_INCLUDE_SOC_SOC_H */
|
