1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
|
/*
* This file is part of the coreboot project.
*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/acpi.h>
#include <soc/southbridge.h>
void pm_write8(u8 reg, u8 value)
{
write8((void *)(PM_MMIO_BASE + reg), value);
}
u8 pm_read8(u8 reg)
{
return read8((void *)(PM_MMIO_BASE + reg));
}
void pm_write16(u8 reg, u16 value)
{
write16((void *)(PM_MMIO_BASE + reg), value);
}
u16 pm_read16(u8 reg)
{
return read16((void *)(PM_MMIO_BASE + reg));
}
void pm_write32(u8 reg, u32 value)
{
write32((void *)(PM_MMIO_BASE + reg), value);
}
u32 pm_read32(u8 reg)
{
return read32((void *)(PM_MMIO_BASE + reg));
}
void smi_write32(uint8_t offset, uint32_t value)
{
write32((void *)(APU_SMI_BASE + offset), value);
}
uint32_t smi_read32(uint8_t offset)
{
return read32((void *)(APU_SMI_BASE + offset));
}
uint16_t smi_read16(uint8_t offset)
{
return read16((void *)(APU_SMI_BASE + offset));
}
void smi_write16(uint8_t offset, uint16_t value)
{
write16((void *)(APU_SMI_BASE + offset), value);
}
uint8_t smi_read8(uint8_t offset)
{
return read8((void *)(APU_SMI_BASE + offset));
}
void smi_write8(uint8_t offset, uint8_t value)
{
write8((void *)(APU_SMI_BASE + offset), value);
}
uint8_t biosram_read8(uint8_t offset)
{
return read8((void *)(BIOSRAM_MMIO_BASE + offset));
}
void biosram_write8(uint8_t offset, uint8_t value)
{
write8((void *)(BIOSRAM_MMIO_BASE + offset), value);
}
/* BiosRam may only be accessed a byte at a time */
uint16_t biosram_read16(uint8_t offset)
{
int i;
uint16_t value = 0;
for (i = sizeof(value) - 1 ; i >= 0 ; i--)
value = (value << 8) | biosram_read8(offset + i);
return value;
}
uint32_t biosram_read32(uint8_t offset)
{
uint32_t value = biosram_read16(offset + sizeof(uint16_t)) << 16;
return value | biosram_read16(offset);
}
void biosram_write16(uint8_t offset, uint16_t value)
{
int i;
for (i = 0 ; i < sizeof(value) ; i++) {
biosram_write8(offset + i, value & 0xff);
value >>= 8;
}
}
void biosram_write32(uint8_t offset, uint32_t value)
{
int i;
for (i = 0 ; i < sizeof(value) ; i++) {
biosram_write8(offset + i, value & 0xff);
value >>= 8;
}
}
uint16_t pm_acpi_pm_cnt_blk(void)
{
return pm_read16(PM1_CNT_BLK);
}
uint16_t pm_acpi_pm_evt_blk(void)
{
return pm_read16(PM_EVT_BLK);
}
void xhci_pm_write8(uint8_t reg, uint8_t value)
{
write8((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value);
}
uint8_t xhci_pm_read8(uint8_t reg)
{
return read8((void *)(XHCI_ACPI_PM_MMIO_BASE + reg));
}
void xhci_pm_write16(uint8_t reg, uint16_t value)
{
write16((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value);
}
uint16_t xhci_pm_read16(uint8_t reg)
{
return read16((void *)(XHCI_ACPI_PM_MMIO_BASE + reg));
}
void xhci_pm_write32(uint8_t reg, uint32_t value)
{
write32((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value);
}
uint32_t xhci_pm_read32(uint8_t reg)
{
return read32((void *)(XHCI_ACPI_PM_MMIO_BASE + reg));
}
int acpi_get_sleep_type(void)
{
return acpi_sleep_from_pm1(inw(pm_acpi_pm_cnt_blk()));
}
void save_uma_size(uint32_t size)
{
biosram_write32(BIOSRAM_UMA_SIZE, size);
}
void save_uma_base(uint64_t base)
{
biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base);
biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32));
}
uint32_t get_uma_size(void)
{
return biosram_read32(BIOSRAM_UMA_SIZE);
}
uint64_t get_uma_base(void)
{
uint64_t base;
base = biosram_read32(BIOSRAM_UMA_BASE);
base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32);
return base;
}
|
