blob: ee6ab91c6d9c88411b7f257428c172b8735807f6 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
|
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/agesawrapper.h>
#include <device/device.h>
#include <soc/pci_devs.h>
static int is_sata_config(void)
{
return !((SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE)
|| (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE));
}
static inline int sb_sata_enable(void)
{
/* True if IDE or AHCI. */
return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) ||
(SataAhci == CONFIG_STONEYRIDGE_SATA_MODE);
}
static inline int sb_ide_enable(void)
{
/* True if IDE or LEGACY IDE. */
return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) ||
(SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE);
}
void SetFchResetParams(FCH_RESET_INTERFACE *params)
{
const struct device *dev = pcidev_path_on_root(SATA_DEVFN);
params->Xhci0Enable = CONFIG(STONEYRIDGE_XHCI_ENABLE);
if (dev && dev->enabled) {
params->SataEnable = sb_sata_enable();
params->IdeEnable = sb_ide_enable();
} else {
params->SataEnable = FALSE;
params->IdeEnable = FALSE;
}
}
void SetFchEnvParams(FCH_INTERFACE *params)
{
const struct device *dev = pcidev_path_on_root(SATA_DEVFN);
params->AzaliaController = AzEnable;
params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE;
if (dev && dev->enabled) {
params->SataEnable = is_sata_config();
params->IdeEnable = !params->SataEnable;
params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE ==
SataLegacyIde);
} else {
params->SataEnable = FALSE;
params->IdeEnable = FALSE;
params->SataIdeMode = FALSE;
}
}
void SetFchMidParams(FCH_INTERFACE *params)
{
SetFchEnvParams(params);
}
|
