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# SPDX-License-Identifier: GPL-2.0-only
config SOC_AMD_STONEYRIDGE
bool
select ACPI_SOC_NVS
select ARCH_X86
select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
select COLLECT_TIMESTAMPS_NO_TSC
select GENERIC_GPIO_LIB
select GENERIC_UDELAY
select HAVE_CF9_RESET
select HAVE_SMI_HANDLER
select HAVE_USBDEBUG_OPTIONS
select PARALLEL_MP_AP_WORK
select RTC
select SOC_AMD_PI
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK_ACPI
select SOC_AMD_COMMON_BLOCK_ACPI_GPIO
select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM
select SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS
select SOC_AMD_COMMON_BLOCK_AOAC
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
select SOC_AMD_COMMON_BLOCK_CAR
select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H
select SOC_AMD_COMMON_BLOCK_HDA
select SOC_AMD_COMMON_BLOCK_I2C
select SOC_AMD_COMMON_BLOCK_IOMMU
select SOC_AMD_COMMON_BLOCK_LPC
select SOC_AMD_COMMON_BLOCK_MCA
select SOC_AMD_COMMON_BLOCK_PCI
select SOC_AMD_COMMON_BLOCK_PM
select SOC_AMD_COMMON_BLOCK_PSP_GEN1
select SOC_AMD_COMMON_BLOCK_SATA
select SOC_AMD_COMMON_BLOCK_SMBUS
select SOC_AMD_COMMON_BLOCK_SMI
select SOC_AMD_COMMON_BLOCK_SMM
select SOC_AMD_COMMON_BLOCK_SMN
select SOC_AMD_COMMON_BLOCK_SPI
select SOC_AMD_COMMON_BLOCK_SVI2
select SOC_AMD_COMMON_BLOCK_UART
select SSE2
select TSC_SYNC_LFENCE
select USE_DDR4
select X86_AMD_FIXED_MTRRS
help
AMD support for SOCs in Family 15h Models 60h-6Fh and Models 70h-7Fh.
if SOC_AMD_STONEYRIDGE
config AMD_APU_STONEYRIDGE
bool
help
AMD Stoney Ridge APU
config AMD_APU_PRAIRIEFALCON
bool
help
AMD Embedded Prairie Falcon APU
config AMD_APU_MERLINFALCON
bool
help
AMD Embedded Merlin Falcon APU
config AMD_APU_PKG_FP4
bool
help
AMD FP4 package
config AMD_APU_PKG_FT4
bool
help
AMD FT4 package
config AMD_SOC_PACKAGE
string
default "FP4" if AMD_APU_PKG_FP4
default "FT4" if AMD_APU_PKG_FT4
config CHIPSET_DEVICETREE
string
default "soc/amd/stoneyridge/chipset_cz.cb" if AMD_APU_MERLINFALCON
default "soc/amd/stoneyridge/chipset_st.cb" if AMD_APU_PRAIRIEFALCON
default "soc/amd/stoneyridge/chipset_st.cb" if AMD_APU_STONEYRIDGE
config VBOOT
select VBOOT_STARTS_IN_BOOTBLOCK
select VBOOT_VBNV_CMOS
select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
# TODO: Sync these with definitions in PI vendorcode.
# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR.
# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE.
config DCACHE_RAM_BASE
hex
default 0x30000
config DCACHE_RAM_SIZE
hex
default 0x10000
config PRERAM_CBFS_CACHE_SIZE
default 0x0
config DCACHE_BSP_STACK_SIZE
hex
default 0x4000
help
The amount of anticipated stack usage in CAR by bootblock and
other stages.
config PRERAM_CBMEM_CONSOLE_SIZE
hex
default 0x1600
help
Increase this value if preram cbmem console is getting truncated
config BOTTOMIO_POSITION
hex "Bottom of 32-bit IO space"
default 0xD0000000
help
If PCI peripherals with big BARs are connected to the system
the bottom of the IO must be decreased to allocate such
devices.
Declare the beginning of the 128MB-aligned MMIO region. This
option is useful when PCI peripherals requesting large address
ranges are present.
config ECAM_MMCONF_BASE_ADDRESS
default 0xF8000000
config ECAM_MMCONF_BUS_NUMBER
default 64
config VGA_BIOS_ID
string
default "1002,9870" if AMD_APU_MERLINFALCON
default "1002,98e0"
help
The default VGA BIOS PCI vendor/device ID should be set to the
result of the map_oprom_vendev() function in northbridge.c.
config VGA_BIOS_FILE
string
default "3rdparty/amd_blobs/stoneyridge/CarrizoGenericVbios.bin" if AMD_APU_MERLINFALCON
default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" if AMD_APU_PRAIRIEFALCON
default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" if AMD_APU_STONEYRIDGE
config S3_VGA_ROM_RUN
bool
default n
config EHCI_BAR
hex
default 0xfef00000
config STONEYRIDGE_XHCI_ENABLE
bool "Enable Stoney Ridge XHCI Controller"
default y
help
The XHCI controller must be enabled and the XHCI firmware
must be added in order to have USB 3.0 support configured
by coreboot. The OS will be responsible for enabling the XHCI
controller if the XHCI firmware is available but the
XHCI controller is not enabled by coreboot.
config STONEYRIDGE_XHCI_FWM
bool "Add xhci firmware"
default y
help
Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0
config STONEYRIDGE_GEC_FWM
bool
default n
help
Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC.
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
config STONEYRIDGE_XHCI_FWM_FILE
string "XHCI firmware path and filename"
default "3rdparty/amd_blobs/stoneyridge/xhci.bin"
depends on STONEYRIDGE_XHCI_FWM
config STONEYRIDGE_GEC_FWM_FILE
string "GEC firmware path and filename"
depends on STONEYRIDGE_GEC_FWM
config AMDFW_CONFIG_FILE
string
string "AMD PSP Firmware config file"
default "src/soc/amd/stoneyridge/fw_cz.cfg" if AMD_APU_MERLINFALCON
default "src/soc/amd/stoneyridge/fw_st.cfg" if AMD_APU_PRAIRIEFALCON
default "src/soc/amd/stoneyridge/fw_st.cfg" if AMD_APU_STONEYRIDGE
config STONEYRIDGE_SATA_MODE
int "SATA Mode"
default 0
range 0 6
help
Select the mode in which SATA should be driven.
The default is NATIVE.
0: NATIVE mode does not require a ROM.
2: AHCI may work with or without AHCI ROM. It depends on the payload support.
For example, seabios does not require the AHCI ROM.
3: LEGACY IDE
4: IDE to AHCI
5: AHCI7804: ROM Required, and AMD driver required in the OS.
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
comment "NATIVE"
depends on STONEYRIDGE_SATA_MODE = 0
comment "AHCI"
depends on STONEYRIDGE_SATA_MODE = 2
comment "LEGACY IDE"
depends on STONEYRIDGE_SATA_MODE = 3
comment "IDE to AHCI"
depends on STONEYRIDGE_SATA_MODE = 4
comment "AHCI7804"
depends on STONEYRIDGE_SATA_MODE = 5
comment "IDE to AHCI7804"
depends on STONEYRIDGE_SATA_MODE = 6
config STONEYRIDGE_LEGACY_FREE
bool "System is legacy free"
help
Select y if there is no keyboard controller in the system.
This sets variables in AGESA and ACPI.
config SERIRQ_CONTINUOUS_MODE
bool
default n
help
Set this option to y for serial IRQ in continuous mode.
Otherwise it is in quiet mode.
config CONSOLE_UART_BASE_ADDRESS
depends on CONSOLE_SERIAL
hex
default 0xfedc6000
config SMM_TSEG_SIZE
hex
default 0x800000 if HAVE_SMI_HANDLER
default 0x0
config SMM_RESERVED_SIZE
hex
default 0x160000
config SMM_MODULE_STACK_SIZE
hex
default 0x800
config ACPI_CPU_STRING
string
default "P%03X"
config ACPI_SSDT_PSD_INDEPENDENT
default n
config ACPI_BERT
bool "Build ACPI BERT Table"
default y
depends on HAVE_ACPI_TABLES
help
Report Machine Check errors identified in POST to the OS in an
ACPI Boot Error Record Table. This option reserves an 8MB region
for building the error structures.
config USE_PSPSECUREOS
bool "Include PSP SecureOS blobs in AMD firmware"
default y
help
Include the PspSecureOs, PspTrustlet and TrustletKey binaries
in the amdfw section.
If unsure, answer 'y'
config SOC_AMD_PSP_SELECTABLE_SMU_FW
bool
default y if AMD_APU_STONEYRIDGE
help
Some ST implementations allow storing SMU firmware into cbfs and
calling the PSP to load the blobs at the proper time.
Merlin Falcon does not support it. If you are using 00670F00 SOC,
ask your AMD representative if it supports it or not.
config SOC_AMD_SMU_FANLESS
bool
depends on SOC_AMD_PSP_SELECTABLE_SMU_FW
default n if SOC_AMD_SMU_NOTFANLESS
default y
config SOC_AMD_SMU_FANNED
bool
depends on SOC_AMD_PSP_SELECTABLE_SMU_FW
default n
select SOC_AMD_SMU_NOTFANLESS
config SOC_AMD_SMU_NOTFANLESS # helper symbol - do not use
bool
depends on SOC_AMD_PSP_SELECTABLE_SMU_FW
config AMDFW_OUTSIDE_CBFS
bool "The AMD firmware is outside CBFS"
default n
help
The AMDFW (PSP) is typically locatable in cbfs. Select this
option to manually attach the generated amdfw.rom outside of
cbfs. The location is selected by the FWM position.
config DIMM_SPD_SIZE
default 512 # DDR4
config RO_REGION_ONLY
string
depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A
default "apu/amdfw"
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int
default 133
config DISABLE_KEYBOARD_RESET_PIN
bool
help
Instruct the SoC to not use the state of GPIO_129 as keyboard reset
signal. When this pin is used as GPIO and the keyboard reset
functionality isn't disabled, configuring it as an output and driving
it as 0 will cause a reset.
config ACPI_BERT_SIZE
hex
default 0x100000 if ACPI_BERT
default 0x0
help
Specify the amount of DRAM reserved for gathering the data used to
generate the ACPI table.
endif # SOC_AMD_STONEYRIDGE
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