1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
|
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpigen.h>
#include <amdblocks/acpi.h>
#include <amdblocks/alib.h>
#include <amdblocks/memmap.h>
#include <amdblocks/ioapic.h>
#include <arch/ioapic.h>
#include <assert.h>
#include <cbmem.h>
#include <console/console.h>
#include <cpu/amd/msr.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <fsp/util.h>
#include <stdint.h>
#include <soc/iomap.h>
#include "chip.h"
#define DPTC_TOTAL_UPDATE_PARAMS 4
struct dptc_input {
uint16_t size;
struct alib_dptc_param params[DPTC_TOTAL_UPDATE_PARAMS];
} __packed;
#define DPTC_INPUTS(_thermctllmit, _sustained, _fast, _slow) \
{ \
.size = sizeof(struct dptc_input), \
.params = { \
{ \
.id = ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID, \
.value = _thermctllmit, \
}, \
{ \
.id = ALIB_DPTC_SUSTAINED_POWER_LIMIT_ID, \
.value = _sustained, \
}, \
{ \
.id = ALIB_DPTC_FAST_PPT_LIMIT_ID, \
.value = _fast, \
}, \
{ \
.id = ALIB_DPTC_SLOW_PPT_LIMIT_ID, \
.value = _slow, \
}, \
}, \
}
/*
*
* +--------------------------------+
* | |
* | |
* | |
* | |
* | |
* | |
* | |
* reserved_dram_end +--------------------------------+
* | |
* | verstage (if reqd) |
* | (VERSTAGE_SIZE) |
* +--------------------------------+ VERSTAGE_ADDR
* | |
* | FSP-M |
* | (FSP_M_SIZE) |
* +--------------------------------+ FSP_M_ADDR
* | romstage |
* | (ROMSTAGE_SIZE) |
* +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END
* | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10
* | bootblock |
* | (C_ENV_BOOTBLOCK_SIZE) |
* +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE
* | Unused hole |
* | (86KiB) |
* +--------------------------------+
* | FMAP cache (FMAP_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
* | Early Timestamp region (512B) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
* | Preram CBMEM console |
* | (PRERAM_CBMEM_CONSOLE_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE
* | PSP shared (vboot workbuf) |
* | (PSP_SHAREDMEM_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE
* | APOB (64KiB) |
* +--------------------------------+ PSP_APOB_DRAM_ADDRESS
* | Early BSP stack |
* | (EARLYRAM_BSP_STACK_SIZE) |
* reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
* | DRAM |
* +--------------------------------+ 0x100000
* | Option ROM |
* +--------------------------------+ 0xc0000
* | Legacy VGA |
* +--------------------------------+ 0xa0000
* | DRAM |
* +--------------------------------+ 0x0
*/
static void read_resources(struct device *dev)
{
uint32_t mem_usable = (uintptr_t)cbmem_top();
unsigned int idx = 0;
const struct hob_header *hob = fsp_get_hob_list();
const struct hob_resource *res;
struct resource *gnb_apic;
uintptr_t early_reserved_dram_start, early_reserved_dram_end;
const struct memmap_early_dram *e = memmap_get_early_dram_usage();
early_reserved_dram_start = e->base;
early_reserved_dram_end = e->base + e->size;
/* The root complex has no PCI BARs implemented, so there's no need to call
pci_dev_read_resources for it */
/* 0x0 - 0x9ffff */
ram_resource(dev, idx++, 0, 0xa0000 / KiB);
/* 0xa0000 - 0xbffff: legacy VGA */
mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
/* 0xc0000 - 0xfffff: Option ROM */
reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
/* 1MB - bottom of DRAM reserved for early coreboot usage */
ram_resource(dev, idx++, (1 * MiB) / KiB,
(early_reserved_dram_start - (1 * MiB)) / KiB);
/* DRAM reserved for early coreboot usage */
reserved_ram_resource(dev, idx++, early_reserved_dram_start / KiB,
(early_reserved_dram_end - early_reserved_dram_start) / KiB);
/* top of DRAM consumed early - low top usable RAM
* cbmem_top() accounts for low UMA and TSEG if they are used. */
ram_resource(dev, idx++, early_reserved_dram_end / KiB,
(mem_usable - early_reserved_dram_end) / KiB);
mmconf_resource(dev, idx++);
if (!hob) {
printk(BIOS_ERR, "%s incomplete because no HOB list was found\n",
__func__);
return;
}
for (; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = fsp_next_hob(hob)) {
if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR)
continue;
res = fsp_hob_header_to_resource(hob);
if (res->type == EFI_RESOURCE_SYSTEM_MEMORY && res->addr < mem_usable)
continue; /* 0 through low usable was set above */
if (res->type == EFI_RESOURCE_MEMORY_MAPPED_IO)
continue; /* Done separately */
if (res->type == EFI_RESOURCE_SYSTEM_MEMORY)
ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
else if (res->type == EFI_RESOURCE_MEMORY_RESERVED)
reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
else
printk(BIOS_ERR, "failed to set resources for type %d\n",
res->type);
}
/* GNB IOAPIC resource */
gnb_apic = new_resource(dev, idx++);
gnb_apic->base = GNB_IO_APIC_ADDR;
gnb_apic->size = 0x00001000;
gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static void root_complex_init(struct device *dev)
{
setup_ioapic((u8 *)GNB_IO_APIC_ADDR, GNB_IOAPIC_ID);
}
static void acipgen_dptci(void)
{
const struct soc_amd_picasso_config *config = config_of_soc();
if (!config->dptc_enable)
return;
struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC,
config->sustained_power_limit_mW,
config->fast_ppt_limit_mW,
config->slow_ppt_limit_mW);
struct dptc_input tablet_mode_input = DPTC_INPUTS(
config->thermctl_limit_tablet_mode_degreeC,
config->sustained_power_limit_tablet_mode_mW,
config->fast_ppt_limit_tablet_mode_mW,
config->slow_ppt_limit_tablet_mode_mW);
acpigen_write_alib_dptc((uint8_t *)&default_input, sizeof(default_input),
(uint8_t *)&tablet_mode_input, sizeof(tablet_mode_input));
}
static void root_complex_fill_ssdt(const struct device *device)
{
acpi_fill_root_complex_tom(device);
acipgen_dptci();
}
static const char *gnb_acpi_name(const struct device *dev)
{
return "GNB";
}
static struct device_operations root_complex_operations = {
.read_resources = read_resources,
.set_resources = noop_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = root_complex_init,
.acpi_name = gnb_acpi_name,
.acpi_fill_ssdt = root_complex_fill_ssdt,
};
static const struct pci_driver family17_root_complex __pci_driver = {
.ops = &root_complex_operations,
.vendor = PCI_VID_AMD,
.device = PCI_DID_AMD_17H_MODEL_101F_NB,
};
|
