blob: 7c13f0863ecc006787245235b28b0dde92cdf34e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
|
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/amd/common/acpi/pci_root.asl>
#include "globalnvs.asl"
/* Power state notification to ALIB */
#include "pnot.asl"
/* Contains the supported sleep states for this chipset */
#include <soc/amd/common/acpi/sleepstates.asl>
/* Contains _SWS methods */
#include <soc/amd/common/acpi/acpi_wake_source.asl>
/* System Bus */
Scope(\_SB) { /* Start \_SB scope */
/* global utility methods expected within the \_SB scope */
#include <arch/x86/acpi/globutil.asl>
ROOT_BRIDGE(PCI0)
Scope(PCI0) {
/* Describe the AMD Northbridge */
#include "northbridge.asl"
/* Describe the AMD Fusion Controller Hub */
#include <soc/amd/common/acpi/lpc.asl>
#include <soc/amd/common/acpi/platform.asl>
}
/* PCI IRQ mapping for the Southbridge */
#include "pci_int_defs.asl"
/* Describe PCI INT[A-H] for the Southbridge */
#include <soc/amd/common/acpi/pci_int.asl>
/* Describe the MMIO devices in the FCH */
#include "mmio.asl"
/* Add GPIO library */
#include <soc/amd/common/acpi/gpio_bank_lib.asl>
#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
#include <soc/amd/common/acpi/dptc.asl>
#endif
} /* End \_SB scope */
|
