1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
|
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <amdblocks/acpimmio_map.h>
#define AOAC_DEVICE(DEV_NAME, DEV_ID, SX) \
PowerResource(DEV_NAME, SX, 0) { \
OperationRegion (AOAC, SystemMemory, ACPIMMIO_BASE(AOAC) + 0x40 + (DEV_ID << 1), 2) \
Field (AOAC, ByteAcc, NoLock, Preserve) { \
/* \
* Target Device State \
* \
* 0 = D0 - Uninitialized \
* 1 = D0 - Initialized \
* 2 = D1/D2/D3Hot \
* 3 = D3Cold \
* \
* This field is only used to cut off register access. It does not \
* control any power states. D3Cold is the only value that will \
* cut off register access. All other values will allow register \
* access and are purely informational. \
*/ \
TDS, 2, \
\
DS, 1, /* Device State - Purely informational */ \
\
/* \
* Power On Dev \
* \
* 1 = Perform hardware sequence to power on the device \
* 0 = Perform hardware sequence to power off the device \
* \
* This register is only valid when Is Software Control = 0. \
*/ \
POD, 1, \
\
/* Software Power On Reset B */ \
SPRB, 1, \
/* Software Ref Clock OK */ \
SRCO, 1, \
/* Software Reset B */ \
SRB, 1, \
/* \
* Is Software Control \
* \
* 1 = Allow software to control Power On Reset B, \
* Ref Clock OK, and Reset B. \
* 0 = Hardware control \
*/ \
ISWC, 1, \
\
/* Power Reset B State */ \
PRBS, 1, \
/* Ref Clock OK State */ \
RCOS, 1, \
/* Reset B State */ \
RBS, 1, \
/* Device Off Gating State */ \
DOGS, 1, \
/* D3 Cold State */ \
D3CS, 1, \
/* Device Clock OK State */ \
COS, 1, \
/* State of device */ \
STA0, 1, \
/* State of device */ \
STA1, 1, \
} \
Method(_STA) { \
Local0 = (PRBS && RCOS && RBS) \
\
If (Local0) { \
Return (1) \
} Else { \
Return (0) \
} \
} \
Method(_ON, 0, Serialized) { \
ISWC=0 \
POD=1 \
\
While (!PRBS || !RCOS || !RBS) { \
Stall (100) \
} \
} \
Method(_OFF, 0, Serialized) { \
ISWC=0 \
POD=0 \
\
While (PRBS || RCOS || RBS) { \
Stall (100) \
} \
} \
Method(_RST, 0, Serialized) { \
ISWC=1 \
SRB=1 \
\
/* Assert the SwRstB signal for 200 us */ \
Stall (200) \
\
SRB=0 \
ISWC=0 \
\
While (!PRBS || !RCOS || !RBS) { \
Printf ("Waiting for device to complete reset") \
Stall (100) \
} \
} \
}
Device (AOAC) {
Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources
Method (_STA, 0x0, NotSerialized)
{
/*
* This case is used to indicate a valid device for which no
* device driver should be loaded (for example, a bridge
* device.) Children of this device may be present and valid.
* OSPM should continue enumeration below a device whose _STA
* returns this bit combination.
*/
Return (0x08)
}
AOAC_DEVICE(I2C2, 7, 0)
AOAC_DEVICE(I2C3, 8, 0)
AOAC_DEVICE(FUR0, 11, 0)
AOAC_DEVICE(FUR1, 12, 0)
AOAC_DEVICE(FUR2, 16, 0)
AOAC_DEVICE(FUR3, 26, 0)
}
|
