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config SOC_AMD_COMMON_BLOCK_PSP
bool
help
This option builds in the Platform Security Processor initialization
functions. Do not select this directly in SoC code, select
SOC_AMD_COMMON_BLOCK_PSP_GENx instead.
config SOC_AMD_COMMON_BLOCK_PSP_GEN1
bool
select SOC_AMD_COMMON_BLOCK_PSP
help
Used by the PSP in AMD systems before family 17h, e.g. stoneyridge.
config SOC_AMD_COMMON_BLOCK_PSP_GEN2
bool
select SOC_AMD_COMMON_BLOCK_PSP
help
Used by the PSP in AMD family 17h, 19h and possibly newer CPUs.
config SOC_AMD_PSP_SELECTABLE_SMU_FW
bool
help
Some PSP implementations allow storing SMU firmware into cbfs and
calling the PSP to load the blobs at the proper time.
The soc/<codename> should select this if its PSP supports the feature
and each mainboard can choose to select an appropriate fanless or
fanned set of blobs. Ask your AMD representative whether your APU
is considered fanless.
config AMD_SOC_SEPARATE_EFS_SECTION
bool
help
Use separate EFS FMAP section instead of putting EFS into CBFS. The
FMAP section must begin exactly at the location the EFS needs to be
placed in the flash. This option can be used to place the EFS right
after the 128kByte EC firmware at the beginning of the flash.
config SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL
bool
default n
depends on SOC_AMD_COMMON_BLOCK_PSP_GEN2
help
Enable sending of set SPL message to PSP. Enable this option if the platform
will require SPL fusing to be performed by PSP.
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