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## SPDX-License-Identifier: GPL-2.0-only
config SOC_AMD_COMMON_BLOCK_CAR
bool
help
This option allows the SOC to use a standard AMD cache-as-ram (CAR)
implementation. CAR setup is built into bootblock and teardown is
in postcar. The teardown procedure does not preserve the stack so
it may not be appropriate for a romstage implementation without
additional consideration. If this option is not used, the SOC must
implement these functions separately.
This is only used for AMD CPU before family 17h. From family 17h on
the RAM is already initialized by the PSP before the x86 cores are
released from reset.
config SOC_AMD_COMMON_BLOCK_NONCAR
bool
select RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT
help
From family 17h on AMD CPUs/APUs don't use cache as RAM (CAR) any
more, since the RAM initialization is already done by the PSP when
the x86 cores are released from reset.
if SOC_AMD_COMMON_BLOCK_NONCAR
config BOOTBLOCK_IN_CBFS
bool
default n
config MEMLAYOUT_LD_FILE
string
default "src/soc/amd/common/block/cpu/noncar/memlayout.ld"
config CBFS_CACHE_SIZE
hex
help
The size of the cbfs_cache region.
config ACPI_CPU_STRING
string
default "C%03X"
config SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
bool
help
Disable the legacy DMA decodes again after the call into the
reference code in romstage to fix up things.
endif # SOC_AMD_COMMON_BLOCK_NONCAR
config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H
bool
help
Select this option to include code to calculate the CPU frequency
from the P state MSR values on AMD CPU families 15h and 16h.
config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
bool
help
Select this option to include code to calculate the CPU frequency
from the P state MSR values on AMD CPU families 17h and 19h.
config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH
bool
help
Select this option to include code to calculate the CPU frequency
from the P state MSR values on AMD CPU family 1Ah.
config SOC_AMD_COMMON_BLOCK_MCA_COMMON
bool
help
Add common machine check architecture support. Do not select this
in the SoC's Kconfig; select either SOC_AMD_COMMON_BLOCK_MCA or
SOC_AMD_COMMON_BLOCK_MCAX which will select this one.
config SOC_AMD_COMMON_BLOCK_MCA
bool
select SOC_AMD_COMMON_BLOCK_MCA_COMMON
help
Add IA32 machine check architecture (MCA) support for pre-Zen CPUs.
config SOC_AMD_COMMON_BLOCK_MCAX
bool
select SOC_AMD_COMMON_BLOCK_MCA_COMMON
help
Add extended machine check architecture (MCAX) support for AMD family
17h, 19h and possibly newer CPUs.
config SOC_AMD_COMMON_BLOCK_SMM
bool
select X86_SMM_SKIP_RELOCATION_HANDLER if HAVE_SMI_HANDLER
help
Add common SMM relocation, finalization and handler functionality to
the build.
config SOC_AMD_COMMON_LATE_SMM_LOCKING
bool
depends on SOC_AMD_COMMON_BLOCK_SMM
help
Select this option to perform SMM locking late in soc_finalize(), rather than earlier
in smm_relocation_handler(). This is required for pre-Zen SoCs like Stoneyridge which
call into an AGESA binary as part of S3 resume, and require SMM to still be unlocked
at that time.
config SOC_AMD_COMMON_BLOCK_SVI2
bool
help
Select this option is the SoC uses the serial VID 2 standard for
encoding the voltage it requests from the VRM.
config SOC_AMD_COMMON_BLOCK_SVI3
bool
help
Select this option is the SoC uses the serial VID 3 standard for
encoding the voltage it requests from the VRM.
config SOC_AMD_COMMON_BLOCK_TSC
bool
select TSC_SYNC_LFENCE
select UDELAY_TSC
select TSC_MONOTONIC_TIMER
help
Select this option to add the common functions for getting the TSC
frequency of AMD family 17h, 19h and 1Ah CPUs/APUs and to provide
TSC-based monotonic timer functionality to the build.
config SOC_AMD_COMMON_BLOCK_CPU_SYNC_PSP_ADDR_MSR
bool
help
Select this option to have coreboot sync the PSP_ADDR_MSR from
the BSP to all APs.
config SOC_AMD_COMMON_BLOCK_UCODE
bool
help
Builds in support for loading uCode.
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