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##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2009 coresystems GmbH
## Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config NORTHBRIDGE_INTEL_X4X
bool
if NORTHBRIDGE_INTEL_X4X
config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
def_bool y
select HAVE_DEBUG_RAM_SETUP
select LAPIC_MONOTONIC_TIMER
select VGA
select INTEL_GMA_ACPI
select CACHE_MRC_SETTINGS
select POSTCAR_STAGE
select POSTCAR_CONSOLE
select SMM_TSEG
select PARALLEL_MP
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
config CBFS_SIZE
hex
default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX
config BOOTBLOCK_NORTHBRIDGE_INIT
string
default "northbridge/intel/x4x/bootblock.c"
config VGA_BIOS_ID
string
default "8086,2e32"
config MMCONF_BASE_ADDRESS
hex
default 0xe0000000
config SMM_RESERVED_SIZE
hex
default 0x100000
endif
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