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/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
#include <arch/bootblock.h>
#include <device/pci_ops.h>
#include "pineview.h"
#define MMCONF_256_BUSSES 16
#define ENABLE 1
void bootblock_early_northbridge_init(void)
{
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR,
CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE);
}
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