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##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config NORTHBRIDGE_INTEL_NEHALEM
bool
select CPU_INTEL_MODEL_2065X
select VGA
select INTEL_EDID
select INTEL_GMA_ACPI
select CACHE_MRC_SETTINGS
select POSTCAR_STAGE
select POSTCAR_CONSOLE
select HAVE_DEBUG_RAM_SETUP
if NORTHBRIDGE_INTEL_NEHALEM
config MMCONF_BUS_NUMBER
int
default 256
config CBFS_SIZE
hex
default 0x100000
config VGA_BIOS_ID
string
default "8086,0046"
config DCACHE_RAM_BASE
hex
default 0xfefc0000
config DCACHE_RAM_SIZE
hex
default 0x10000
config BOOTBLOCK_NORTHBRIDGE_INIT
string
default "northbridge/intel/nehalem/bootblock.c"
config MRC_CACHE_SIZE
hex
default 0x10000
endif
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