1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
|
/* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h>
#include <console/console.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <elog.h>
#include <cpu/x86/msr.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/turbo.h>
#include <arch/cpu.h>
#include "ironlake.h"
static void ironlake_setup_bars(void)
{
/* Setting up Southbridge. In the northbridge code. */
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
/* Enable ACPI BAR */
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80);
printk(BIOS_DEBUG, " done.\n");
printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
/* No reset */
RCBA32(GCS) = RCBA32(GCS) | (1 << 5);
/* halt timer */
outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);
/* halt timer */
outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06);
printk(BIOS_DEBUG, " done.\n");
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
/* Set up all hardcoded northbridge BARs */
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, 0);
pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, 0);
pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, 0);
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(0), 0x30);
pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(1), 0x33);
pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(2), 0x33);
pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(3), 0x33);
pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(4), 0x33);
pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33);
pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33);
printk(BIOS_DEBUG, " done.\n");
}
static void early_cpu_init(void)
{
msr_t m;
/* bit 0 = disable multicore,
bit 1 = disable quadcore,
bit 8 = disable hyperthreading. */
pci_update_config32(PCI_DEV(0xff, 0x00, 0), 0x80, 0xfffffefc, 0x10000);
u8 reg8;
struct cpuid_result result;
result = cpuid_ext(0x6, 0x8b);
if (!(result.eax & 0x2)) {
m = rdmsr(MSR_FSB_CLOCK_VCC);
reg8 = ((m.lo & 0xff00) >> 8) + 1;
m = rdmsr(IA32_PERF_CTL);
m.lo = (m.lo & ~0xff) | reg8;
wrmsr(IA32_PERF_CTL, m);
m = rdmsr(IA32_MISC_ENABLE);
m.hi &= ~0x00000040;
m.lo |= 0x10000;
wrmsr(IA32_MISC_ENABLE, m);
}
m = rdmsr(MSR_FSB_CLOCK_VCC);
reg8 = ((m.lo & 0xff00) >> 8) + 1;
m = rdmsr(IA32_PERF_CTL);
m.lo = (m.lo & ~0xff) | reg8;
wrmsr(IA32_PERF_CTL, m);
m = rdmsr(IA32_MISC_ENABLE);
m.lo |= 0x10000;
wrmsr(IA32_MISC_ENABLE, m);
}
void ironlake_early_initialization(int chipset_type)
{
u32 capid0_a;
u8 reg8;
int s3_resume;
/* Device ID Override Enable should be done very early */
capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4);
if (capid0_a & (1 << 10)) {
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3);
reg8 &= ~7; /* Clear 2:0 */
if (chipset_type == IRONLAKE_MOBILE)
reg8 |= 1; /* Set bit 0 */
pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8);
}
/* Setup all BARs required for early PCIe and raminit */
ironlake_setup_bars();
s3_resume = (inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
(((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3);
elog_boot_notify(s3_resume);
/* Device Enable */
pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, DEVEN_IGD | DEVEN_PEG10 | DEVEN_HOST);
early_cpu_init();
pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR);
pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
/* Magic for S3 resume. Must be done early. */
if (s3_resume) {
MCHBAR32(0x1e8) = (MCHBAR32(0x1e8) & ~1) | 6;
MCHBAR32(0x1e8) = (MCHBAR32(0x1e8) & ~3) | 4;
}
}
|
