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##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2009 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config NORTHBRIDGE_INTEL_I945
bool
if NORTHBRIDGE_INTEL_I945
config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
def_bool y
select HAVE_DEBUG_RAM_SETUP
select LAPIC_MONOTONIC_TIMER
select VGA
select INTEL_GMA_ACPI
select INTEL_GMA_SSC_ALTERNATE_REF
select INTEL_EDID
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select POSTCAR_STAGE
select POSTCAR_CONSOLE
select SMM_TSEG
select PARALLEL_MP
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
def_bool n
config NORTHBRIDGE_INTEL_SUBTYPE_I945GM
def_bool n
config BOOTBLOCK_NORTHBRIDGE_INIT
string
default "northbridge/intel/i945/bootblock.c"
config VGA_BIOS_ID
string
default "8086,27a2" if NORTHBRIDGE_INTEL_SUBTYPE_I945GM
default "8086,2772" if NORTHBRIDGE_INTEL_SUBTYPE_I945GC
config I945_LVDS
def_bool n
select MAINBOARD_HAS_NATIVE_VGA_INIT
select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
help
Selected by mainboards that use native graphics initialization
for the LVDS port. A linear framebuffer is only supported for
LVDS.
config CHANNEL_XOR_RANDOMIZATION
bool
default n
config MMCONF_BASE_ADDRESS
hex
default 0xf0000000
config OVERRIDE_CLOCK_DISABLE
bool
default n
help
Usually system firmware turns off system memory clock
signals to unused SO-DIMM slots to reduce EMI and power
consumption.
However, some boards do not like unused clock signals to
be disabled.
config MAXIMUM_SUPPORTED_FREQUENCY
int
default 0
help
If non-zero, this designates the maximum DDR frequency
the board supports, despite what the chipset should be
capable of.
config CHECK_SLFRCS_ON_RESUME
def_bool n
help
On some boards it may be neccessary to hard reset early
during resume from S3 if the SLFRCS register indicates that
a memory channel is not guaranteed to be in self-refresh.
On other boards the check always creates a false positive,
effectively making it impossible to resume.
config SMM_RESERVED_SIZE
hex
default 0x100000
endif
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