blob: b767f5081e7a266f95b257d13e87638c78ca88c3 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Arastra, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
/* This code is based on src/northbridge/intel/e7520/raminit.h */
#ifndef NORTHBRIDGE_INTEL_I3100_RAMINIT_H
#define NORTHBRIDGE_INTEL_I3100_RAMINIT_H
#define DIMM_SOCKETS 4
struct mem_controller {
u32 node_id;
device_t f0, f1, f2, f3;
u16 channel0[DIMM_SOCKETS];
u16 channel1[DIMM_SOCKETS];
};
void sdram_initialize(int controllers, const struct mem_controller *ctrl);
#endif
|
