blob: b6cfd0b65d8bcf5b6c72e07a97bb287ca1635e1e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
|
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
#include <arch/bootblock.h>
#include <device/pci_ops.h>
#include "haswell.h"
void bootblock_early_northbridge_init(void)
{
uint32_t reg;
/*
* The "io" variant of the config access is explicitly used to setup the PCIEXBAR
* because CONFIG_MMCONF_SUPPORT is set to true. That way, all subsequent
* non-explicit config accesses use MCFG. This code also assumes that
* bootblock_northbridge_init() is the first thing called in the non-asm
* boot block code. The final assumption is that no assembly code is using
* the CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
reg = 0;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, reg);
reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
}
|
