blob: f9c68f34dd27bf800dc273b892a70e438cef5916 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
|
##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config NORTHBRIDGE_INTEL_HASWELL
bool
select CPU_INTEL_HASWELL
select CACHE_MRC_SETTINGS
select INTEL_DDI
select INTEL_GMA_ACPI
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
select POSTCAR_STAGE
select POSTCAR_CONSOLE
if NORTHBRIDGE_INTEL_HASWELL
config VBOOT
select VBOOT_STARTS_IN_ROMSTAGE
config BOOTBLOCK_NORTHBRIDGE_INIT
string
default "northbridge/intel/haswell/bootblock.c"
config VGA_BIOS_ID
string
default "8086,0166"
config CACHE_MRC_SIZE_KB
int
default 512
config DCACHE_RAM_BASE
hex
default 0xff7c0000
config DCACHE_RAM_SIZE
hex
default 0x10000
help
The size of the cache-as-ram region required during bootblock
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
must add up to a power of 2.
config DCACHE_RAM_MRC_VAR_SIZE
hex
default 0x30000
help
The amount of cache-as-ram region required by the reference code.
config HAVE_MRC
bool "Add a System Agent binary"
help
Select this option to add a System Agent binary to
the resulting coreboot image.
Note: Without this binary coreboot will not work
config MRC_FILE
string "Intel System Agent path and filename"
depends on HAVE_MRC
default "mrc.bin"
help
The path and filename of the file to use as System Agent
binary.
config PRE_GRAPHICS_DELAY
int "Graphics initialization delay in ms"
default 0
help
On some systems, coreboot boots so fast that connected monitors
(mostly TVs) won't be able to wake up fast enough to talk to the
VBIOS. On those systems we need to wait for a bit before executing
the VBIOS.
endif
|