1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
|
/* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <console/console.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include "gm45.h"
static void init_egress(void)
{
/* VC0: TC0 only */
epbar_clrbits8(EPVC0RCTL, ~1);
epbar_clrsetbits8(EPPVCCAP1, 7, 1);
/* VC1: isoch */
epbar_write32(EPVC1MTS, 0x0a0a0a0a);
epbar_clrsetbits32(EPVC1RCAP, 127 << 16, 0x0a << 16);
/* VC1: ID1, TC7 */
epbar_clrsetbits32(EPVC1RCTL, 7 << 24, 1 << 24);
epbar_clrsetbits8(EPVC1RCTL, ~1, 1 << 7);
/* VC1 ARB table: setup and enable */
epbar_write32(EP_PORTARB(0), 0x55555555);
epbar_write32(EP_PORTARB(1), 0x55555555);
epbar_write32(EP_PORTARB(2), 0x55555555);
epbar_write32(EP_PORTARB(3), 0x55555555);
epbar_write32(EP_PORTARB(4), 0x55555555);
epbar_write32(EP_PORTARB(5), 0x55555555);
epbar_write32(EP_PORTARB(6), 0x55555555);
epbar_write32(EP_PORTARB(7), 0x00005555);
epbar_setbits32(EPVC1RCTL, 1 << 16);
do {} while ((epbar_read8(EPVC1RSTS) & 1) != 0);
/* VC1: enable */
epbar_setbits32(EPVC1RCTL, 1 << 31);
do {} while ((epbar_read8(EPVC1RSTS) & 2) != 0);
}
/* MCH side */
/* b2step: b2 stepping or higher */
static void init_dmi(int b2step)
{
/* VC0: TC0 only */
dmibar_clrbits8(DMIVC0RCTL, ~1);
dmibar_clrsetbits8(DMIPVCCAP1, 7, 1);
/* VC1: ID1, TC7 */
dmibar_clrsetbits32(DMIVC1RCTL, 7 << 24, 1 << 24);
dmibar_clrsetbits8(DMIVC1RCTL, ~1, 1 << 7);
/* VC1: enable */
dmibar_setbits32(DMIVC1RCTL, 1 << 31);
do {} while ((dmibar_read8(DMIVC1RSTS) & VC1NP) != 0);
/* additional configuration. */
dmibar_setbits32(0x200, 3 << 13);
dmibar_clrbits32(0x200, 1 << 21);
dmibar_clrsetbits32(0x200, 3 << 26, 2 << 26);
dmibar_write32(0x2c, 0x86000040);
dmibar_setbits32(0xfc, 1 << 0);
dmibar_setbits32(0xfc, 1 << 1);
dmibar_setbits32(0xfc, 1 << 4);
if (!b2step) {
dmibar_setbits32(0xfc, 1 << 11);
} else {
dmibar_clrbits32(0xfc, 1 << 11);
}
dmibar_clrbits32(0x204, 3 << 10);
dmibar_clrbits32(0xf4, 1 << 4);
dmibar_setbits32(0xf0, 3 << 24);
dmibar_write32(0xf04, 0x07050880);
dmibar_write32(0xf44, 0x07050880);
dmibar_write32(0xf84, 0x07050880);
dmibar_write32(0xfc4, 0x07050880);
/* lock down write-once registers
DMIBAR32(0x84) will be set in setup_aspm(). */
dmibar_setbits32(0x308, 0);
dmibar_setbits32(0x314, 0);
dmibar_setbits32(0x324, 0);
dmibar_setbits32(0x328, 0);
dmibar_setbits32(0x334, 0);
dmibar_setbits32(0x338, 0);
}
static void init_pcie(const int peg_enabled,
const int sdvo_enabled,
const int peg_x16)
{
const pci_devfn_t mch = PCI_DEV(0, 0, 0);
const pci_devfn_t pciex = PCI_DEV(0, 1, 0);
printk(BIOS_DEBUG, "PEG x%d %s, SDVO %s\n", peg_x16?16:1,
peg_enabled?"enabled":"disabled",
sdvo_enabled?"enabled":"disabled");
if (peg_enabled) {
pci_or_config8(mch, D0F0_DEVEN, 1 << 1);
pci_write_config8(pciex, 0x224,
(pci_read_config8(pciex, 0x224) & ~31) | (peg_x16 ? 16 : 0) | 1);
pci_and_config16(pciex, 0x224, ~(1 << 8));
/* FIXME: fill in: slot or fixed? -> devicetree */
int peg_is_slot = 0;
if (peg_is_slot) {
pci_or_config16(pciex, PEG_CAP, 1 << 8);
}
/* FIXME: fill in: slot number, slot power -> devicetree */
/* Use slot number 0 by now, slots on sb count from 1. */
int peg_slot = 0; /* unique within chassis */
/* peg_power := val * 10^-exp */
int peg_power_val = 75;
int peg_power_exp = 0; /* 0..3 */
const u32 tmp = (peg_slot << 17) | (peg_power_exp << 15) | (peg_power_val << 7);
pci_write_config32(pciex, SLOTCAP, tmp);
/* GPEs */
pci_or_config8(pciex, PEGLC, 7);
/* VC0: TC0 only, VC0 only */
pci_and_config8(pciex, D1F0_VC0RCTL, 1);
pci_and_config8(pciex, D1F0_VCCAP, ~7);
}
}
static void setup_aspm(const stepping_t stepping, const int peg_enabled)
{
u32 tmp32;
const pci_devfn_t pciex = PCI_DEV(0, 1, 0);
/* Prerequisites for ASPM: */
if (peg_enabled) {
pci_or_config32(pciex, 0x200, 3 << 13);
pci_and_config32(pciex, 0x0f0, ~((1 << 27) | (1 << 26)));
pci_or_config32(pciex, 0x0f0, 3 << 24);
pci_and_config32(pciex, 0x0f4, ~(1 << 4));
pci_or_config32(pciex, 0x0fc, 1 << 0);
pci_or_config32(pciex, 0x0fc, 1 << 1);
pci_or_config32(pciex, 0x0fc, 1 << 4);
pci_and_config32(pciex, 0x0fc, ~(7 << 5));
/* Set L0s, L1 supported in LCTL? */
pci_or_config32(pciex, 0x0b0, 3 << 0);
pci_or_config32(pciex, 0x0f0, 3 << 24);
tmp32 = pci_read_config32(pciex, 0x0f0);
if ((stepping >= STEPPING_B0) && (stepping <= STEPPING_B1))
tmp32 |= (1 << 31);
else if (stepping >= STEPPING_B2)
tmp32 &= ~(1 << 31);
pci_write_config32(pciex, 0x0f0, tmp32);
tmp32 = pci_read_config32(pciex, 0x0fc);
if ((stepping >= STEPPING_B0) && (stepping <= STEPPING_B1))
tmp32 |= (1 << 10);
else if (stepping >= STEPPING_B2)
tmp32 &= ~(1 << 10);
pci_write_config32(pciex, 0x0fc, tmp32);
tmp32 = pci_read_config32(pciex, 0x0fc);
if (stepping >= STEPPING_B2)
tmp32 |= (1 << 14);
pci_write_config32(pciex, 0x0fc, tmp32);
tmp32 = pci_read_config32(pciex, 0x0fc);
if (stepping >= STEPPING_B1)
tmp32 &= ~(1 << 13);
pci_write_config32(pciex, 0x0fc, tmp32);
}
dmibar_setbits8(0x0e1c, 1 << 0);
dmibar_setbits16(0x0f00, 3 << 8);
dmibar_setbits16(0x0f00, 7 << 3);
dmibar_clrbits32(0x0f14, 1 << 17);
dmibar_clrbits16(0x0e1c, 1 << 8);
if (stepping >= STEPPING_B0) {
dmibar_clrsetbits32(0x0e28 + 4, 0xf << (52 - 32), 0xd << (52 - 32));
dmibar_write32(0x0e2c, 0x88d07333);
}
if (peg_enabled) {
pci_and_config32(pciex, 0xa08, ~(1 << 15));
pci_or_config32(pciex, 0xa84, 1 << 8);
pci_and_config32(pciex, 0xb14, ~(1 << 17));
pci_or_config32(pciex, 0xb00, 3 << 8);
pci_or_config32(pciex, 0xb00, 7 << 3);
pci_and_config32(pciex, 0xa84, ~(1 << 8));
pci_or_config32(pciex, 0xa84, 1 << 8);
pci_update_config32(pciex, 0xb04, ~(0x1f << 23), 0x0e << 23);
pci_or_config32(pciex, 0xb04, 1 << 31);
pci_update_config32(pciex, 0xb04, ~(0x03 << 29), 0x01 << 29);
}
/*\ Setup ASPM on DMI \*/
/* Exit latencies should be checked to be supported by
the endpoint (ICH), but ICH doesn't give any limits. */
if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0)))
dmibar_setbits8(DMILCTL, 3 << 0); // enable ASPM L0s, L1 (write-once)
else
dmibar_setbits8(DMILCTL, 1 << 0); // enable ASPM L0s (write-once)
/* timing */
dmibar_clrsetbits32(DMILCAP, 63 << 12, 2 << 12 | 2 << 15);
dmibar_write8(0x208 + 3, 0);
dmibar_clrbits32(0x208, 3 << 20);
/*\ Setup ASPM on PEG \*/
/*
* Maybe we just have to advertise ASPM through LCAP[11:10]
* (LCAP[17:15] == 010b is the default, will be locked, as it's R/WO),
* set 0x208[31:24,23:22] to zero, 0x224[24:21] = 1 and let the
* generic ASPM code do the rest? - Nico
*/
/* TODO: Prepare PEG for ASPM. */
}
static void setup_rcrb(const int peg_enabled)
{
/*\ RCRB setup: Egress Port \*/
/* Set component ID of MCH (1). */
epbar_write8(EPESD + 2, 1);
/* Link1: component ID 1, link valid. */
epbar_clrsetbits32(EPLE1D, 0xffffff, 1 << 16 | 1 << 0);
epbar_write32(EPLE1A, CONFIG_FIXED_DMIBAR_MMIO_BASE);
if (peg_enabled)
/* Link2: link_valid. */
epbar_setbits8(EPLE2D, 1 << 0); /* link valid */
/*\ RCRB setup: DMI Port \*/
/* Set component ID of MCH (1). */
dmibar_write8(DMIESD + 2, 1);
/* Link1: target port 0, component id 2 (ICH), link valid. */
dmibar_write32(DMILE1D, 0 << 24 | 2 << 16 | 1 << 0);
dmibar_write32(DMILE1A, CONFIG_FIXED_RCBA_MMIO_BASE);
/* Link2: component ID 1 (MCH), link valid */
dmibar_clrsetbits32(DMILE2D, 0xffffff, 1 << 16 | 1 << 0);
dmibar_write32(DMILE2A, CONFIG_FIXED_MCHBAR_MMIO_BASE);
}
void gm45_late_init(const stepping_t stepping)
{
const pci_devfn_t mch = PCI_DEV(0, 0, 0);
const int peg_enabled = (pci_read_config8(mch, D0F0_DEVEN) >> 1) & 1;
const int sdvo_enabled = mchbar_read16(0x40) >> 8 & 1;
const int peg_x16 = (peg_enabled && !sdvo_enabled);
init_egress();
init_dmi(stepping >= STEPPING_B2);
init_pcie(peg_enabled, sdvo_enabled, peg_x16);
setup_aspm(stepping, peg_enabled);
setup_rcrb(peg_enabled);
}
|
