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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/pci_ops.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include "gm45.h"
void gm45_early_init(void)
{
const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0);
/* Setup MCHBAR. */
pci_write_config32(d0f0, D0F0_MCHBAR_LO, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1);
/* Setup DMIBAR. */
pci_write_config32(d0f0, D0F0_DMIBAR_LO, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1);
/* Setup EPBAR. */
pci_write_config32(d0f0, D0F0_EPBAR_LO, CONFIG_FIXED_EPBAR_MMIO_BASE | 1);
pci_write_config32(d0f0, D0F0_PMBASE, DEFAULT_PMBASE | 1);
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(d0f0, D0F0_PAM(0), 0x30);
pci_write_config8(d0f0, D0F0_PAM(1), 0x33);
pci_write_config8(d0f0, D0F0_PAM(2), 0x33);
pci_write_config8(d0f0, D0F0_PAM(3), 0x33);
pci_write_config8(d0f0, D0F0_PAM(4), 0x33);
pci_write_config8(d0f0, D0F0_PAM(5), 0x33);
pci_write_config8(d0f0, D0F0_PAM(6), 0x33);
}
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