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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <bootstate.h>
#include <device/pci.h>
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
/* Need pci1234 array
* pci1234[0] will record sblink and bus range
* pci1234[i] will record ht chain i.
* It will keep the sequence when some ht io card is not installed.
*
* 1n: 8
* 2n: 7x2
* 3n: 6x3
* 4n: 5x4
* 5n: 4x5
* 6n: 3x6
* 7n: 2x7
* 8n: 1x8
*
* 8n(4x2): 8x4
* 16n(4x4): 16*2
* 20n(4x5): 20x1
* 32n(4x4+4x4): 16x1
*
* Total: xxx: I just want to use 32 instead, If you have more, you may need to
* reset HC_POSSIBLE_NUM and update ssdt.dsl (hcdn, hclk)
*
* Put all the possible ht node/link to the list tp pci1234[] in get_bus_conf.c
* on MB dir. How about co-processor on socket 1 on 2 way system.
* or socket 2, and socket3 on 4 way system? treat that as one hc too!
*
*/
#include "northbridge.h"
void get_pci1234(void)
{
int i,j;
u32 dword;
dword = sysconf.sblk<<8;
dword |= 1;
sysconf.pci1234[0] = dword; // sblink
sysconf.hcid[0] = 0;
/* about hardcode numbering for HT_IO support
set the node_id and link_id that could have ht chain in the one array,
then check if is enabled.... then update final value
*/
//here we need to set hcdn
//1. hypertransport.c need to record hcdn_reg together with 0xe0, 0xe4, 0xe8, 0xec when are set
//2. so at the same time we need update hsdn with hcdn_reg here
for (j = 0; j < sysconf.ht_c_num; j++) {
u32 dwordx;
dwordx = sysconf.ht_c_conf_bus[j];
dwordx &=0xfffffffd; //keep bus num, node_id, link_num, enable bits
if ((dwordx & 0x7fd) == dword) { //SBLINK
sysconf.pci1234[0] = dwordx;
sysconf.hcdn[0] = sysconf.hcdn_reg[j];
continue;
}
if ((dwordx & 1)) {
// We need to find out the number of HC
// for exact match
for (i = 1; i < sysconf.hc_possible_num; i++) {
if ((dwordx & 0x7fc) == (sysconf.pci1234[i] & 0x7fc)) { // same node and same linkn
sysconf.pci1234[i] = dwordx;
sysconf.hcdn[i] = sysconf.hcdn_reg[j];
break;
}
}
// for 0xffc match or same node
for (i = 1; i < sysconf.hc_possible_num; i++) {
if ((dwordx & 0x7fc) == (dwordx & sysconf.pci1234[i] & 0x7fc)) {
sysconf.pci1234[i] = dwordx;
sysconf.hcdn[i] = sysconf.hcdn_reg[j];
break;
}
}
}
}
for (i = 1; i < sysconf.hc_possible_num; i++) {
if (!(sysconf.pci1234[i] & 1)) {
sysconf.pci1234[i] = 0;
sysconf.hcdn[i] = 0x20202020;
}
sysconf.hcid[i] = 0;
}
}
void get_default_pci1234(int mb_hc_possible)
{
int i;
for (i = 0; i < mb_hc_possible; i++) {
sysconf.pci1234[i] = 0x0000ffc;
sysconf.hcdn[i] = 0x20202020;
}
sysconf.hc_possible_num = mb_hc_possible;
get_pci1234();
}
static void amd_bs_sysconf(void *arg)
{
/* Prepare sysconf structures, which are used to generate IRQ,
* MP and ACPI table entries.
*/
get_bus_conf();
}
BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, amd_bs_sysconf, NULL);
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