1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "early_ht.h"
#include <stdint.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
// For SB HT chain only
// mmconf is not ready yet
void set_bsp_node_CHtExtNodeCfgEn(void)
{
#if CONFIG(EXT_RT_TBL_SUPPORT)
u32 dword;
dword = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x68);
dword |= (1<<27) | (1<<25);
/* CHtExtNodeCfgEn: coherent link extended node configuration enable,
Nodes[31:0] will be 0xff:[31:0], Nodes[63:32] will be 0xfe:[31:0]
---- 32 nodes now only
It can be used even nodes less than 8 nodes.
We can have 8 more device on bus 0 in that case
*/
/* CHtExtAddrEn */
pci_io_write_config32(PCI_DEV(0, 0x18, 0), 0x68, dword);
// CPU on bus 0xff and 0xfe now. For now on we can use CONFIG_CBB and CONFIG_CDB.
#endif
}
void enumerate_ht_chain(void)
{
#if CONFIG_HT_CHAIN_UNITID_BASE != 0
/* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain),
if so, don't need to go through the chain */
/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
* On most boards this just happens. If a CPU has multiple
* non Coherent links the appropriate bus registers for the
* links needs to be programed to point at bus 0.
*/
unsigned next_unitid, last_unitid = 0;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
// let't record the device of last ht device, So we can set the
// Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
unsigned real_last_unitid = 0;
u8 real_last_pos = 0;
int ht_dev_num = 0; // except host_bridge
u8 end_used = 0;
#endif
next_unitid = CONFIG_HT_CHAIN_UNITID_BASE;
do {
u32 id;
u8 hdr_type, pos;
last_unitid = next_unitid;
id = pci_io_read_config32(PCI_DEV(0,0,0), PCI_VENDOR_ID);
/* If the chain is enumerated quit */
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0x0000))
{
break;
}
hdr_type = pci_io_read_config8(PCI_DEV(0,0,0), PCI_HEADER_TYPE);
pos = 0;
hdr_type &= 0x7f;
if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
(hdr_type == PCI_HEADER_TYPE_BRIDGE))
{
pos = pci_io_read_config8(PCI_DEV(0,0,0), PCI_CAPABILITY_LIST);
}
while (pos != 0) {
u8 cap;
cap = pci_io_read_config8(PCI_DEV(0,0,0), pos + PCI_CAP_LIST_ID);
if (cap == PCI_CAP_ID_HT) {
u16 flags;
/* Read and write and reread flags so the link
* direction bit is valid.
*/
flags = pci_io_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS);
pci_io_write_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS, flags);
flags = pci_io_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS);
if ((flags >> 13) == 0) {
unsigned count;
unsigned ctrl, ctrl_off;
pci_devfn_t devx;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
if (next_unitid >= 0x18) {
if (!end_used) {
next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE;
end_used = 1;
} else {
goto out;
}
}
real_last_unitid = next_unitid;
real_last_pos = pos;
ht_dev_num++;
#endif
#if !CONFIG_HT_CHAIN_END_UNITID_BASE
if (!next_unitid)
goto out;
#endif
flags &= ~0x1f;
flags |= next_unitid & 0x1f;
count = (flags >> 5) & 0x1f;
devx = PCI_DEV(0, next_unitid, 0);
next_unitid += count;
pci_io_write_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS, flags);
/* Test for end of chain */
ctrl_off = ((flags >> 10) & 1)?
PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
do {
ctrl = pci_io_read_config16(devx, pos + ctrl_off);
/* Is this the end of the hypertransport chain? */
if (ctrl & (1 << 6)) {
goto out;
}
if (ctrl & ((1 << 4) | (1 << 8))) {
/*
* Either the link has failed, or we have
* a CRC error.
* Sometimes this can happen due to link
* retrain, so lets knock it down and see
* if its transient
*/
ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
pci_io_write_config16(devx, pos + ctrl_off, ctrl);
ctrl = pci_io_read_config16(devx, pos + ctrl_off);
if (ctrl & ((1 << 4) | (1 << 8))) {
// can not clear the error
break;
}
}
} while ((ctrl & (1 << 5)) == 0);
break;
}
}
pos = pci_io_read_config8(PCI_DEV(0, 0, 0), pos + PCI_CAP_LIST_NEXT);
}
} while (last_unitid != next_unitid);
out: ;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
if ((ht_dev_num > 1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) {
u16 flags;
flags = pci_io_read_config16(PCI_DEV(0,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
flags &= ~0x1f;
flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;
pci_io_write_config16(PCI_DEV(0, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);
}
#endif
#endif
}
|
