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chip northbridge/intel/e7520 # mch
device domain 0 on
subsystemid 0x15d9 0x5580 inherit
chip southbridge/intel/i82801ex # i82801er
# USB ports
device pci 1d.0 on end
device pci 1d.1 on end
device pci 1d.2 on end
device pci 1d.3 on end
device pci 1d.7 on end
# -> VGA
device pci 1e.0 on end
# -> IDE
device pci 1f.0 on
chip superio/winbond/w83627hf
device pnp 2e.0 off end
device pnp 2e.2 on
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 on
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.4 off end
device pnp 2e.5 off end
device pnp 2e.6 off end
device pnp 2e.7 off end
device pnp 2e.9 off end
device pnp 2e.a on end
device pnp 2e.b off end
end
end
device pci 1f.1 on end
device pci 1f.2 on end
device pci 1f.3 on end
register "pirq_a_d" = "0x0b070a05"
register "pirq_e_h" = "0x0a808080"
end
device pci 00.0 on end
device pci 00.1 on end
device pci 01.0 on end
device pci 02.0 on end
device pci 03.0 on
chip southbridge/intel/pxhd # pxhd1
# Bus bridges and ioapics usually bus 2
device pci 0.0 on end
device pci 0.1 on end
device pci 0.2 on
# On board gig e1000
chip drivers/generic/generic
device pci 02.0 on end
device pci 02.1 on end
end
end
device pci 0.3 on end
end
end
device pci 04.0 on
chip southbridge/intel/pxhd # pxhd2
# Bus bridges and ioapics usually bus 5
device pci 0.0 on end
# Slot 6 is usually 6:2.0
device pci 0.1 on end
device pci 0.2 on end
# Slot 7 is usually 7:2.0
device pci 0.3 on end
end
end
device pci 06.0 on end
end
device cpu_cluster 0 on
chip cpu/intel/socket_mPGA604 # cpu 0
device lapic 0 on end
end
chip cpu/intel/socket_mPGA604 # cpu 1
device lapic 6 on end
end
end
register "intrline" = "0x00070105"
end
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