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chip soc/intel/cannonlake
# CPU
# Enable Enhanced Intel SpeedStep
register "eist_enable" = "1"
# Graphics
# IGD Displays
register "panel_cfg" = "{
.up_delay_ms = 0, // T3
.backlight_on_delay_ms = 0, // T7
.backlight_off_delay_ms = 0, // T9
.down_delay_ms = 0, // T10
.cycle_delay_ms = 500, // T12
.backlight_pwm_hz = 200, // PWM
}"
# FSP Memory
register "enable_c6dram" = "1"
register "SaGv" = "SaGv_Enabled"
# FSP Silicon
# Serial I/O
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoSkipInit,
[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
}"
# Power
register "PchPmSlpS3MinAssert" = "2" # 50ms
register "PchPmSlpS4MinAssert" = "3" # 1s
register "PchPmSlpSusMinAssert" = "3" # 500ms
register "PchPmSlpAMinAssert" = "3" # 2s
# PM Util
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
register "gpe0_dw0" = "PMC_GPP_B"
register "gpe0_dw1" = "PMC_GPP_C"
register "gpe0_dw2" = "PMC_GPP_E"
# PCIe Clock
register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
# Actual device tree.
device cpu_cluster 0 on end
device domain 0 on
device ref system_agent on end
device ref igpu on end
device ref dptf on
register "Device4Enable" = "1"
end
device ref thermal off end
device ref ufs off end
device ref gspi2 off end
device ref xhci on
# Motherboard USB Type C
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"
# Motherboard USB 3.0
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"
# Daughterboard SD Card
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"
# Daughterboard USB 3.0
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"
# Webcam
register "usb2_ports[CONFIG_CCD_PORT]" = "USB2_PORT_MID(OC_SKIP)"
# Internal Bluetooth
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"
end
device ref xdci off end
device ref shared_sram on end
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
end
device ref sdxc off end
device ref i2c0 on
chip drivers/i2c/hid
register "generic.hid" = ""STAR0001""
register "generic.desc" = ""Touchpad""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x20"
device i2c 2c on end
end
end
device ref i2c1 off end
device ref i2c2 off end
device ref i2c3 off end
device ref heci1 on end
device ref heci2 off end
device ref csme_ider off end
device ref csme_ktr off end
device ref heci3 off end
device ref heci4 off end
device ref sata on
register "SataSalpSupport" = "1"
# Port 1
register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[1]" = "1"
end
device ref i2c4 on end
device ref i2c5 off end
device ref uart2 on end
device ref emmc off end
device ref pcie_rp1 off end
device ref pcie_rp2 off end
device ref pcie_rp3 off end
device ref pcie_rp4 off end
device ref pcie_rp5 off end
device ref pcie_rp6 off end
device ref pcie_rp7 off end
device ref pcie_rp8 off end
device ref pcie_rp9 on # SSD x4
register "PcieRpSlotImplemented[8]" = "1"
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[1]" = "0x08"
register "PcieClkSrcClkReq[1]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
end
device ref pcie_rp10 off end
device ref pcie_rp11 off end
device ref pcie_rp12 off end
device ref uart0 off end
device ref uart1 off end
device ref gspi0 off end
device ref gspi1 off end
device ref lpc_espi on
register "gen1_dec" = "0x000c0681"
register "gen2_dec" = "0x000c1641"
register "gen3_dec" = "0x00fc0201"
register "gen4_dec" = "0x000c0081"
chip ec/starlabs/merlin
# Port pair 4Eh/4Fh
device pnp 4e.00 on end # IO Interface
device pnp 4e.01 off end # Com 1
device pnp 4e.02 off end # Com 2
device pnp 4e.04 off end # System Wake-Up
device pnp 4e.05 off end # PS/2 Mouse
device pnp 4e.06 on # PS/2 Keyboard
io 0x60 = 0x0060
io 0x62 = 0x0064
irq 0x70 = 1
end
device pnp 4e.0a off end # Consumer IR
device pnp 4e.0f off end # Shared Memory/Flash Interface
device pnp 4e.10 off end # RTC-like Timer
device pnp 4e.11 off end # Power Management Channel 1
device pnp 4e.12 off end # Power Management Channel 2
device pnp 4e.13 off end # Serial Peripheral Interface
device pnp 4e.14 off end # Platform EC Interface
device pnp 4e.17 off end # Power Management Channel 3
device pnp 4e.18 off end # Power Management Channel 4
device pnp 4e.19 off end # Power Management Channel 5
end
end
device ref p2sb on end
device ref pmc hidden end
device ref hda on
register "PchHdaAudioLinkHda" = "1"
end
device ref smbus on end
device ref fast_spi on end
device ref gbe off end
end
chip drivers/crb
device mmio 0xfed40000 on end
end
end
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