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##
## This file is part of the coreboot project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
## Copyright (C) 2010 Siemens AG, Inc.
## (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
##
##
entries
#start-bit length config config-ID name
#0 8 r 0 seconds
#8 8 r 0 alarm_seconds
#16 8 r 0 minutes
#24 8 r 0 alarm_minutes
#32 8 r 0 hours
#40 8 r 0 alarm_hours
#48 8 r 0 day_of_week
#56 8 r 0 day_of_month
#64 8 r 0 month
#72 8 r 0 year
# =======================================================
#80 4 r 0 rate_select
#84 3 r 0 REF_Clock
#87 1 r 0 UIP
# =======================================================
#88 1 r 0 auto_switch_DST
#89 1 r 0 24_hour_mode
#90 1 r 0 binary_values_enable
#91 1 r 0 square-wave_out_enable
#92 1 r 0 update_finished_enable
#93 1 r 0 alarm_interrupt_enable
#94 1 r 0 periodic_interrupt_enable
#95 1 r 0 disable_clock_updates
# ========================================================
#96 288 r 0 temporary_filler
0 384 r 0 reserved_memory
# ========================================================
#384 1 r 0 unused
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
385 1 e 4 last_boot
#386 2 r 1 unused
388 4 r 0 reboot_bits
392 3 e 5 baud_rate
#395 1 r 1 unused
#396 1 r 1 unused
#397 2 r 8 unused
399 1 e 2 multi_core
#400 8 r 18 reserved
408 4 e 6 debug_level
412 1 e 1 power_on_after_fail
#413 1 r 1 unused
414 1 e 17 sata_mode
415 1 e 1 nmi
416 1 e 1 cpu_fan_control
417 1 e 1 chassis_fan_control
418 1 e 13 cpu_fan_polarity
419 1 e 13 chassis_fan_polarity
420 4 e 14 cpu_t_min
424 4 e 14 cpu_t_max
428 4 e 15 cpu_dutycycle_min
432 4 e 15 cpu_dutycycle_max
436 4 e 14 chassis_t_min
440 4 e 14 chassis_t_max
444 4 e 15 chassis_dutycycle_min
448 4 e 15 chassis_dutycycle_max
#452 4 r 9 unused
456 4 e 10 boot_delay
460 4 e 11 lcd_panel_id
#===========================================================
464 512 s 0 boot_devices
976 8 h 0 boot_default
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
5 0 115200
5 1 57600
5 2 38400
5 3 19200
5 4 9600
5 5 4800
5 6 2400
5 7 1200
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
#7 0 Network
#7 1 HDD
#7 2 Floppy
#7 8 Fallback_Network
#7 9 Fallback_HDD
#7 10 Fallback_Floppy
#7 3 ROM
8 0 DDR400
8 1 DDR333
8 2 DDR266
8 3 DDR200
# boot delay
10 0 off
10 1 1s
10 2 2s
10 3 3s
10 4 4s
10 5 5s
10 6 6s
10 7 7s
10 8 8s
10 9 9s
10 10 10s
# LCD Panel ID
11 0 no_panel
11 1 1024x768_65MHz_Dual
11 2 1920x1200_162MHz
11 3 1600x1200_162MHz
11 4 1024x768_65MHz
11 5 1400x1050_108MHz
11 6 1680x1050_119MHz
11 7 2048x1536_164MHz
11 8 1280x1024_108MHz
11 9 1366x768_86MHz_chimei_V32B1L01
# TV Standard
#12 0 NTSC
#12 1 PAL
#12 2 PALM
#12 3 PAL60
#12 4 NTSCJ
#12 5 PALCN
#12 6 PALN
#12 9 SCART-RGB
#12 15 no_tv
# CPU/Chassis FAN Control: polarity
13 0 Active_high
13 1 Active_low
# Temperature °C
14 0 30
14 1 35
14 2 40
14 3 45
14 4 50
14 5 55
14 6 60
14 7 65
14 8 70
14 9 75
14 10 80
14 11 85
14 12 90
14 13 95
14 14 100
# Dutycycle %
15 0 25%
15 1 30%
15 2 35%
15 3 40%
15 4 45%
15 5 50%
15 6 55%
15 7 60%
15 8 65%
15 9 70%
15 10 75%
15 11 80%
15 12 85%
15 13 90%
15 14 95%
15 15 100%
# sata_mode
17 0 AHCI
17 1 IDE
# reserved
18 32 2000
# ==============================
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