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chip northbridge/intel/sandybridge
# IGD Displays
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
# Enable DisplayPort Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
# Enable Panel as LVDS and configure power delays
register "gpu_panel_port_select" = "PANEL_PORT_LVDS"
register "gpu_panel_power_cycle_delay" = "5" # T4: 400ms
register "gpu_panel_power_up_delay" = "400" # T1+T2: 40ms
register "gpu_panel_power_down_delay" = "150" # T3: 15ms
register "gpu_panel_power_backlight_on_delay" = "2100" # T5: 210ms
register "gpu_panel_power_backlight_off_delay" = "2100" # TD: 210ms
# Set backlight PWM values
register "gpu_cpu_backlight" = "0x000001e8"
register "gpu_pch_backlight" = "0x03d00000"
register "max_mem_clock_mhz" = "666"
device cpu_cluster 0 on
chip cpu/intel/model_206ax
# Magic APIC ID to locate this chip
device lapic 0 on end
device lapic 0xacac off end
register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1)
register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3)
register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7)
end
end
device domain 0 on
ioapic_irq 4 INTA 0x10
ioapic_irq 4 INTB 0x11
ioapic_irq 4 INTC 0x12
ioapic_irq 4 INTD 0x13
subsystemid 0x1ae0 0xc000 inherit
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "alt_gp_smi_en" = "0x0002"
register "gpi1_routing" = "1"
register "gpi7_routing" = "2"
register "sata_port_map" = "0x1"
# EC range is 0xa00-0xa3f
register "gen1_dec" = "0x003c0a01"
register "gen2_dec" = "0x003c0b01"
register "gen3_dec" = "0x00fc1601"
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 19.0 off end # Intel Gigabit Ethernet
device pci 1a.0 on # USB2 EHCI #2
ioapic_irq 4 INTA 0x11
end
device pci 1b.0 on # High Definition Audio
ioapic_irq 4 INTA 0x16
end
device pci 1c.0 on end # PCIe Port #1 (WLAN)
device pci 1c.1 off end # PCIe Port #2
device pci 1c.2 off end # PCIe Port #3
device pci 1c.3 on # PCIe Port #4 (LAN)
# ioapic_irq 4 INTA 0x13
end
device pci 1c.4 off end # PCIe Port #5
device pci 1c.5 off end # PCIe Port #6
device pci 1c.6 off end # PCIe Port #7
device pci 1c.7 off end # PCIe Port #8
device pci 1d.0 on # USB2 EHCI #1
ioapic_irq 4 INTA 0x13
end
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on # LPC bridge
ioapic_irq 4 INTA 0x10
chip superio/smsc/mec1308
device pnp 2e.1 on # PM1
io 0x60 = 0xb00
end
device pnp 2e.2 off end # EC1
device pnp 2e.3 off end # EC2
device pnp 2e.4 off end # UART
device pnp 2e.7 on # KBC
irq 0x70 = 1
end
device pnp 2e.8 on # EC0
io 0x60 = 0x62
end
device pnp 2e.9 on # MBX
io 0x60 = 0xa00
end
end
chip ec/smsc/mec1308
register "mailbox_port" = "0xa00"
device pnp ff.1 off end
end
chip drivers/generic/ioapic
register "have_isa_interrupts" = "1"
register "base" = "(void *)0xfec00000"
device ioapic 4 on end
end
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
device pci 1f.2 on # SATA Controller 1
ioapic_irq 4 INTA 0x10
end
device pci 1f.3 on # SMBus
ioapic_irq 4 INTC 0x17
end
device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 on end # Thermal
end
end
end
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