1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
Scope (_GPE)
{
/* The event numbers correspond to the bit numbers in the
* GPE0_EN register PMBASE + 0x28.
*/
/* IMO we don't need empty Methods here. If we don't specify
one and don't set the GPE0_EN bit Linux won't neither enable
it. - Nico */
// Thermal Event - original BIOS doesn't have it
Method (_L00, 0)
{
/* FIXME: We should enable throttling here. */
}
// Hot Plug
Method (_L01, 0)
{
}
// USB1
Method (_L03, 0)
{
}
// USB2
Method (_L04, 0)
{
}
// USB5
Method (_L05, 0)
{
}
// _L06 TCOSCI
// SMBus Wake Status
Method (_L07, 0)
{
}
// COM1/COM2 (RI)
Method (_L08, 0)
{
}
// PCIe
Method (_L09, 0)
{
}
// _L0A BatLow / Quick Resume
// PME
Method (_L0B, 0)
{
}
// USB3
Method (_L0C, 0)
{
}
// PME B0
Method (_L0D, 0)
{
}
// USB4
Method (_L0E, 0)
{
}
// _L10 - _L1f: GPIn
// GPI8
Method (_L18, 0)
{
}
// USB6
Method (_L20, 0)
{
}
}
|
