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##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2009 coresystems GmbH
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
chip northbridge/intel/i945
# IGD Displays
register "gfx.ndid" = "3"
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
device cpu_cluster 0 on
chip cpu/intel/socket_m
device lapic 0 on end
end
end
register "pci_mmio_size" = "768"
device domain 0 on
subsystemid 0x4352 0x6886 inherit
device pci 00.0 on end # host bridge
# auto detection:
#device pci 01.0 off end # i945 PCIe root port
device pci 02.0 on end # vga controller
device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx
register "pirqa_routing" = "0x0b"
register "pirqb_routing" = "0x0b"
register "pirqc_routing" = "0x0b"
register "pirqd_routing" = "0x0b"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x0b"
register "pirqh_routing" = "0x0b"
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "gpi13_routing" = "2"
register "gpi8_routing" = "1"
register "gpi7_routing" = "2"
register "gpe0_en" = "0x20800007"
register "c3_latency" = "0x23"
register "docking_supported" = "1"
register "p_cnt_throttling_supported" = "1"
register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED"
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"
register "gen1_dec" = "0x001c02e1" # COM3, COM4
register "gen2_dec" = "0x00fc0601" # ??
register "gen3_dec" = "0x00040069" # EC decode ??
device pci 1b.0 off end # High Definition Audio
device pci 1c.0 on end # PCIe port 1
device pci 1c.1 off end # PCIe port 2
device pci 1c.2 off end # PCIe port 3
device pci 1c.3 on end # PCIe port 4
device pci 1c.4 off end # PCIe port 5
device pci 1c.5 off end # PCIe port 6
device pci 1d.0 on end # USB UHCI
device pci 1d.1 on end # USB UHCI
device pci 1d.2 on end # USB UHCI
device pci 1d.3 on end # USB UHCI
device pci 1d.7 on end # USB2 EHCI
device pci 1e.0 on # PCI bridge
chip southbridge/ti/pci7420
register "smartcard_enabled" = "0x0"
device pci 3.0 on end
device pci 3.1 on end
device pci 3.2 on end
device pci 3.3 off end # smartcard
end
end
device pci 1e.2 on end # AC'97 Audio
device pci 1e.3 off end # AC'97 Modem
device pci 1f.0 on # LPC bridge
chip superio/smsc/lpc47n227
device pnp 2e.1 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 5
end
device pnp 2e.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 off # Keyboard+Mouse
# io 0x60 = 0x60
# io 0x62 = 0x64
# irq 0x70 = 1
# irq 0x72 = 12
end
end
chip superio/renesas/m3885x
device pnp ff.1 on # dummy address
end
end
chip ec/acpi
end
end
device pci 1f.1 off end # IDE
device pci 1f.2 on end # SATA
device pci 1f.3 on end # SMBus
end
end
end
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