1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
|
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
#include <soc/gpe.h>
#include <soc/gpio.h>
/*
* Bidirectional GPIO port when both RX and TX buffer is enabled
* todo: move this macros to src/soc/intel/common/block/include/intelblocks/gpio_defs.h
*/
#ifndef PAD_CFG_GPIO_BIDIRECT
#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \
_PAD_CFG_STRUCT(pad, \
PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \
PAD_BUF(NO_DISABLE) | val, \
PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own))
#endif
#ifndef __ACPI__
/* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI),
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
PAD_CFG_GPI_APIC_HIGH(GPP_A11, NONE, DEEP),
PAD_CFG_GPO(GPP_A12, 1, PWROK),
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1),
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
PAD_CFG_GPO(GPP_A22, 1, DEEP),
PAD_CFG_GPI_APIC_HIGH(GPP_A23, NONE, DEEP),
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST),
PAD_CFG_GPO(GPP_B4, 1, DEEP),
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
PAD_NC(GPP_B8, NONE),
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
PAD_NC(GPP_B10, NONE),
PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP),
PAD_CFG_GPO(GPP_B15, 0, DEEP),
PAD_NC(GPP_B16, NONE),
PAD_CFG_GPI_SCI(GPP_B17, DN_20K, DEEP, EDGE_SINGLE, INVERT),
PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT),
PAD_NC(GPP_B19, NONE),
PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1),
PAD_CFG_NF(GPP_B21, DN_20K, DEEP, NF1),
PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1),
PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1),
PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP),
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
PAD_CFG_GPI_APIC_LOW(GPP_C5, DN_20K, DEEP),
PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, LEVEL, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, LEVEL, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, LEVEL, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, LEVEL, ACPI),
PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
PAD_CFG_GPI_SCI(GPP_E0, NONE, DEEP, EDGE_SINGLE, INVERT),
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),
PAD_CFG_GPIO_BIDIRECT(GPP_E3, 0, NONE, DEEP, LEVEL, ACPI),
PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1),
PAD_CFG_GPI_SCI(GPP_E5, NONE, PLTRST, EDGE_SINGLE, INVERT),
PAD_CFG_GPO(GPP_E6, 0, DEEP),
PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, NONE, IOAPIC, SCI),
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
PAD_CFG_GPO(GPP_E9, 0, DEEP),
PAD_CFG_TERM_GPO(GPP_E10, 1, DN_20K, DEEP),
PAD_CFG_TERM_GPO(GPP_E11, 1, DN_20K, DEEP),
PAD_NC(GPP_E12, NONE),
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT),
PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT),
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1),
PAD_CFG_GPI_APIC_LOW(GPP_E22, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_E23, 0, DN_20K, PLTRST),
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),
PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1),
PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1),
PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1),
PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF2),
PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF2),
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI),
PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI),
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
PAD_CFG_GPI_APIC_HIGH(GPP_F23, NONE, DEEP),
PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, ACPI),
};
#endif /* __ACPI__ */
#endif /* MAINBOARD_GPIO_H */
|
