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##
## This file is part of the coreboot project.
##
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
chip northbridge/intel/ironlake
# IGD Displays
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
register "gpu_dp_b_hotplug" = "0x04"
register "gpu_dp_c_hotplug" = "0x04"
register "gpu_dp_d_hotplug" = "0x04"
# Enable Panel as LVDS and configure power delays
register "gpu_panel_port_select" = "0" # LVDS
register "gpu_panel_power_cycle_delay" = "6"
register "gpu_panel_power_up_delay" = "300"
register "gpu_panel_power_down_delay" = "300"
register "gpu_panel_power_backlight_on_delay" = "3000"
register "gpu_panel_power_backlight_off_delay" = "3000"
register "gpu_cpu_backlight" = "0x58d"
register "gpu_pch_backlight" = "0x061a061a"
device cpu_cluster 0 on
chip cpu/intel/model_2065x
device lapic 0 on end
end
end
register "pci_mmio_size" = "2048"
device domain 0 on
device pci 00.0 on # Host bridge
subsystemid 0x1025 0x0379
end
device pci 01.0 off end # PEG
device pci 02.0 on # VGA controller
subsystemid 0x1025 0x0379
end
chip southbridge/intel/ibexpeak
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "gpi7_routing" = "2"
register "gpi8_routing" = "2"
register "sata_port_map" = "0x11"
register "gpe0_en" = "0x01800046"
register "alt_gp_smi_en" = "0x0000"
register "gen1_dec" = "0x040069"
device pci 16.0 off end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R, only management boot
device pci 16.3 off end # Management Engine KT
device pci 19.0 off end # Ethernet
device pci 1a.0 on # USB2 EHCI
subsystemid 0x1025 0x0379
end
device pci 1b.0 on # Audio Controller
subsystemid 0x1025 0x0379
end
device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 on end # PCIe Port #2
device pci 1c.2 off end
device pci 1c.3 off end
device pci 1c.4 off end
device pci 1c.5 off end
device pci 1c.6 off end
device pci 1c.7 off end
device pci 1d.0 on # USB2 EHCI
subsystemid 0x1025 0x0379
end
device pci 1e.0 on end # PCI 2 PCI bridge
device pci 1f.0 on # PCI-LPC bridge
subsystemid 0x1025 0x0379
end
device pci 1f.2 on # IDE/SATA
subsystemid 0x1025 0x0379
end
device pci 1f.3 on # SMBUS
subsystemid 0x1025 0x0379
end
device pci 1f.4 off end
device pci 1f.5 off end
device pci 1f.6 off end
end
end
end
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