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## SPDX-License-Identifier: GPL-2.0-or-later
chip soc/intel/xeon_sp/skx
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
register "pirqc_routing" = "PCH_IRQ11"
register "pirqd_routing" = "PCH_IRQ11"
register "pirqe_routing" = "PCH_IRQ11"
register "pirqf_routing" = "PCH_IRQ11"
register "pirqg_routing" = "PCH_IRQ11"
register "pirqh_routing" = "PCH_IRQ11"
# configure device interrupt routing
register "ir00_routing" = "0x3210" # IR00, Dev31
register "ir01_routing" = "0x3210" # IR01, Dev30
register "ir02_routing" = "0x3210" # IR02, Dev29
register "ir03_routing" = "0x3210" # IR03, Dev28
register "ir04_routing" = "0x3210" # IR04, Dev27
# configure interrupt polarity control
register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow
register "ipc1" = "0x00000000" # IPC1
register "ipc2" = "0x00000000" # IPC2
register "ipc3" = "0x00000000" # IPC3
# configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs
# FB production turbo_ratio_limit is 0x1f1f1f2022222325
register "turbo_ratio_limit" = "0x1b1b1b1d20222325"
# FB production turbo_ratio_limit_cores is 0x1c1812100c080402
register "turbo_ratio_limit_cores" = "0x1c1814100c080402"
# configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL
register "pstate_req_ratio" = "0xa"
# configure VTD
register "vtd_support" = "1"
register "coherency_support" = "1"
register "ats_support" = "1"
register "gen2_dec" = "0x000c0ca1" # IPMI KCS
device cpu_cluster 0 on end
device domain 0 on
device gpio 0 alias pch_gpio on end
device pci 00.0 on end # Host bridge
device pci 04.0 on end # Intel Corporation SkyLake-E CBDMA Registers
device pci 04.1 on end # Intel Corporation SkyLake-E CBDMA Registers
device pci 04.2 on end # Intel Corporation SkyLake-E CBDMA Registers
device pci 04.3 on end # Intel Corporation SkyLake-E CBDMA Registers
device pci 04.4 on end # Intel Corporation SkyLake-E CBDMA Registers
device pci 04.5 on end # Intel Corporation SkyLake-E CBDMA Registers
device pci 04.6 on end # Intel Corporation SkyLake-E CBDMA Registers
device pci 04.7 on end # Intel Corporation SkyLake-E CBDMA Registers
device pci 05.0 on end # Intel Corporation SkyLake-E MM/Vt-d Configuration Registers
device pci 05.2 on end # Intel Corporation Device 2025
device pci 05.4 on end # Intel Corporation Device 2026
device pci 08.0 on end # Intel Corporation SkyLake-E Ubox Registers
device pci 08.1 on end # Intel Corporation SkyLake-E Ubox Registers
device pci 08.2 on end # Intel Corporation SkyLake-E Ubox Registers
device pci 11.0 on end # Intel Corporation C620 Series Chipset Family MROM 0
device pci 11.1 on end # Intel Corporation C620 Series Chipset Family MROM 1
device pci 11.5 on end # Intel Corporation C620 Series Chipset Family SSATA Controller [AHCI mode]
device pci 14.0 on end # Intel Corporation C620 Series Chipset Family USB 3.0 xHCI Controller
device pci 16.0 on end # Intel Corporation C620 Series Chipset Family MEI Controller #1
device pci 16.1 on end # Intel Corporation C620 Series Chipset Family MEI Controller #2
device pci 16.4 on end # Intel Corporation C620 Series Chipset Family MEI Controller #3
device pci 17.0 on end # Intel Corporation C620 Series Chipset Family SATA Controller [AHCI mode]
device pci 1c.0 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #1
device pci 1c.4 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #5
device pci 1f.0 on
chip drivers/ipmi # BMC KCS
device pnp ca2.0 on end
use pch_gpio as gpio_dev
register "bmc_i2c_address" = "0x20"
register "bmc_boot_timeout" = "90"
register "post_complete_gpio" = "GPP_B20"
register "post_complete_invert" = "1"
end
chip drivers/ipmi/ocp # OCP specific IPMI porting
device pnp ca2.1 on end
end
end # Intel Corporation C621 Series Chipset LPC/eSPI Controller
device pci 1f.1 hidden end # p2sb
device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller
device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus
device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller
end
end
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